Branch starts

feature/baseCAN
Oleg 2 months ago
parent eee4c90277
commit 34fe93213f

@ -1,184 +0,0 @@
/*
// TI File $Revision: /main/11 $
// Checkin $Date: April 15, 2009 09:57:28 $
//###########################################################################
//
// FILE: 28335_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28335 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28335 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} > RAML0, PAGE = 0
#else
ramfuncs : > RAML0, PAGE = 0
#endif
#endif
.text : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

@ -1,23 +1,24 @@
#include "CAN.h" #include "CAN.h"
#include <cstddef>
CAN::CAN(){ CAN::CAN(){
} }
void CAN::initGpio(CAN_VARIANT canVarinat){ void CAN::initGpio(CAN_VARIANT canVarinat){
if(canVarinat == CAN_VARIAN::CANA) InitECanaGpio(); if(canVarinat == CANA) InitECanaGpio();
else if (canVarinat == CAN_VARIAN::CANB) InitECanbGpio(); else if (canVarinat == CANB) InitECanbGpio();
} }
void CAN::config(CAN_VARIANT canVarinat, Uint16 baudrate){ void CAN::config(CAN_VARIANT canVarinat, Uint16 baudrate){
if (CAN == CANA){ if (canVarinat == CANA){
EALLOW; EALLOW;
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1; SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1;
EDIS; EDIS;
p_CanRegs_ = &ECanaRegs; p_CanRegs_ = &ECanaRegs;
p_CanMBoxes_ = &ECanaMboxes; p_CanMBoxes_ = &ECanaMboxes;
} }
else if (CAN == CANB){ else if (canVarinat == CANB){
EALLOW; EALLOW;
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1; SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1;
EDIS; EDIS;
@ -33,154 +34,237 @@ void CAN::config(CAN_VARIANT canVarinat, Uint16 baudrate){
// contents or return false data. This is especially true while writing // contents or return false data. This is especially true while writing
// to/reading from a bit (or group of bits) among bits 16 - 31 // to/reading from a bit (or group of bits) among bits 16 - 31
// //
struct ECAN_REGS ECanShadow; // struct ECAN_REGS ECanShadow;
EALLOW; // EALLOW enables access to protected bits EALLOW; // EALLOW enables access to protected bits
// //
// Configure eCAN RX and TX pins for CAN operation using eCAN regs // Configure eCAN RX and TX pins for CAN operation using eCAN regs
// //
ECanShadow.CANTIOC.all = p_CanRegs_.CANTIOC.all; CanShadow_.CANTIOC.all = p_CanRegs_->CANTIOC.all;
ECanShadow.CANTIOC.bit.TXFUNC = 1; CanShadow_.CANTIOC.bit.TXFUNC = 1;
p_CanRegs_.CANTIOC.all = ECanShadow.CANTIOC.all; p_CanRegs_->CANTIOC.all = CanShadow_.CANTIOC.all;
ECanShadow.CANRIOC.all = p_CanRegs_.CANRIOC.all; CanShadow_.CANRIOC.all = p_CanRegs_->CANRIOC.all;
ECanShadow.CANRIOC.bit.RXFUNC = 1; CanShadow_.CANRIOC.bit.RXFUNC = 1;
p_CanRegs_.CANRIOC.all = ECanShadow.CANRIOC.all; p_CanRegs_->CANRIOC.all = CanShadow_.CANRIOC.all;
// //
// Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
// HECC mode also enables time-stamping feature // HECC mode also enables time-stamping feature
// //
ECanShadow.CANMC.all = p_CanRegs_.CANMC.all; CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
ECanShadow.CANMC.bit.SCB = 1; CanShadow_.CANMC.bit.SCB = 1;
p_CanRegs_.CANMC.all = ECanShadow.CANMC.all; p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
// //
// Initialize all bits of 'Master Control Field' to zero // Initialize all bits of 'Master Control Field' to zero
// Some bits of MSGCTRL register come up in an unknown state. For proper // Some bits of MSGCTRL register come up in an unknown state. For proper
// operation, all bits (including reserved bits) of MSGCTRL must be // operation, all bits (including reserved bits) of MSGCTRL must be
// initialized to zero // initialized to zero
// p_CanMBoxes_->MBOX0.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX0.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX1.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX1.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX2.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX2.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX3.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX3.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX4.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX4.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX5.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX5.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX6.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX6.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX7.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX7.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX8.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX8.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX9.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX9.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX10.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX10.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX11.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX11.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX12.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX12.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX13.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX13.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX14.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX14.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX15.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX15.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX16.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX16.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX17.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX17.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX18.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX18.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX19.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX19.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX20.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX20.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX21.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX21.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX22.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX22.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX23.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX23.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX24.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX24.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX25.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX25.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX26.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX26.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX27.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX27.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX28.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX28.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX29.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX29.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX30.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX30.MSGCTRL.all = 0x00000000; p_CanMBoxes_->MBOX31.MSGCTRL.all = 0x00000000;
p_CanMBoxes_.MBOX31.MSGCTRL.all = 0x00000000;
// //
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution. // as a matter of precaution.
// //
p_CanRegs_.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits p_CanRegs_->CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
p_CanRegs_.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits p_CanRegs_->CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
p_CanRegs_.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits p_CanRegs_->CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
p_CanRegs_.CANGIF1.all = 0xFFFFFFFF; p_CanRegs_->CANGIF1.all = 0xFFFFFFFF;
// //
// Configure bit timing parameters for eCANA // Configure bit timing parameters for eCANA
// //
ECanShadow.CANMC.all = p_CanRegs_.CANMC.all; CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
ECanShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 CanShadow_.CANMC.bit.CCR = 1 ; // Set CCR = 1
p_CanRegs_.CANMC.all = ECanShadow.CANMC.all; p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
CanShadow_.CANMC.bit.DBO = 1 ; // Set DBO = 1
p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
ECanShadow.CANES.all = p_CanRegs_.CANES.all; CanShadow_.CANES.all = p_CanRegs_->CANES.all; //todo Что за строка?
do do { CanShadow_.CANES.all = p_CanRegs_->CANES.all; }
{ while(CanShadow_.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set
ECanShadow.CANES.all = p_CanRegs_.CANES.all;
} while(ECanShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set
ECanShadow.CANBTC.all = 0; CanShadow_.CANBTC.all = 0;
// The following block for all 150 MHz SYSCLKOUT // The following block for all 150 MHz SYSCLKOUT
// (75 MHz CAN clock) - default. Bit rate = 1 Mbps // (75 MHz CAN clock) - default. Bit rate = 1 Mbps / 500 kbps / 250 kbps / 100 kbps
// //
switch (baudrate) { switch (baudrate) {
case : 1000 case 1000:
ECanShadow.CANBTC.bit.BRPREG = 4; CanShadow_.CANBTC.bit.BRPREG = 4;
ECanShadow.CANBTC.bit.TSEG2REG = 3; CanShadow_.CANBTC.bit.TSEG2REG = 3;
ECanShadow.CANBTC.bit.TSEG1REG = 9; CanShadow_.CANBTC.bit.TSEG1REG = 9;
break; break;
case : 500 case 500:
ECanShadow.CANBTC.bit.BRPREG = 9; CanShadow_.CANBTC.bit.BRPREG = 9;
ECanShadow.CANBTC.bit.TSEG2REG = 3; CanShadow_.CANBTC.bit.TSEG2REG = 3;
ECanShadow.CANBTC.bit.TSEG1REG = 9; CanShadow_.CANBTC.bit.TSEG1REG = 9;
break; break;
case : 250 case 250:
ECanShadow.CANBTC.bit.BRPREG = 19; CanShadow_.CANBTC.bit.BRPREG = 19;
ECanShadow.CANBTC.bit.TSEG2REG = 3; CanShadow_.CANBTC.bit.TSEG2REG = 3;
ECanShadow.CANBTC.bit.TSEG1REG = 9; CanShadow_.CANBTC.bit.TSEG1REG = 9;
break; break;
case : 100 case 100:
ECanShadow.CANBTC.bit.BRPREG = 49; CanShadow_.CANBTC.bit.BRPREG = 49;
ECanShadow.CANBTC.bit.TSEG2REG = 3; CanShadow_.CANBTC.bit.TSEG2REG = 3;
ECanShadow.CANBTC.bit.TSEG1REG = 9; CanShadow_.CANBTC.bit.TSEG1REG = 9;
break; break;
default: return; default: return;
} }
ECanShadow.CANBTC.bit.SAM = 1; CanShadow_.CANBTC.bit.SAM = 1;
p_CanRegs_.CANBTC.all = ECanShadow.CANBTC.all; p_CanRegs_->CANBTC.all = CanShadow_.CANBTC.all;
ECanShadow.CANMC.all = p_CanRegs_.CANMC.all; CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
ECanShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 CanShadow_.CANMC.bit.CCR = 0 ; // Set CCR = 0
p_CanRegs_.CANMC.all = ECanShadow.CANMC.all; p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
ECanShadow.CANES.all = p_CanRegs_.CANES.all; CanShadow_.CANES.all = p_CanRegs_->CANES.all;
do do { CanShadow_.CANES.all = p_CanRegs_->CANES.all; }
{ while(CanShadow_.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared
ECanShadow.CANES.all = p_CanRegs_.CANES.all;
} while(ECanShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared
// //
// Disable all Mailboxes // Disable all Mailboxes
// //
p_CanRegs_.CANME.all = 0; // Required before writing the MSGIDs p_CanRegs_->CANME.all = 0; // Required before writing the MSGIDs
CanShadow_.CANTRR.all = p_CanRegs_->CANTRR.all;
CanShadow_.CANTRR.bit.TRR0 = 1;
p_CanRegs_->CANTRR.all = CanShadow_.CANTRR.all;
CanShadow_.CANTRS.all = p_CanRegs_->CANTRS.all;
do {CanShadow_.CANTRS.all = p_CanRegs_->CANTRS.all;}
while(CanShadow_.CANTRS.bit.TRS0 != 0); // Wait for TRS bit to be cleared
//
// Debug feature
// Configure the eCAN for self test mode.
//
CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
CanShadow_.CANMC.bit.STM = 1; // Configure CAN for self-test mode
p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
EDIS; EDIS;
}
void CAN::configTxMBoxes(){
// Write to the MSGID field
p_CanMBoxes_->MBOX1.MSGID.all = 0x0; // IDE-0, AME-0, AAM-0
p_CanMBoxes_->MBOX1.MSGID.bit.STDMSGID = 0xAAA;
p_CanMBoxes_->MBOX1.MSGCTRL.bit.DLC = 8; // Data length in bytes (0-8)
p_CanMBoxes_->MBOX1.MSGCTRL.bit.RTR = 0; // Remote Transmission Request
CanShadow_.CANMD.all = p_CanRegs_->CANMD.all;
CanShadow_.CANMD.bit.MD1 = 0; // Mailbox direction - transmit
p_CanRegs_->CANMD.all = CanShadow_.CANMD.all;
CanShadow_.CANME.all = p_CanRegs_->CANME.all;
CanShadow_.CANME.bit.ME1 = 1;
p_CanRegs_->CANME.all = CanShadow_.CANME.all;
}
void CAN::configRxMBoxes(){
// Write to the MSGID field
p_CanMBoxes_->MBOX25.MSGID.all = 0x0;
p_CanMBoxes_->MBOX25.MSGID.bit.STDMSGID = 0xAAA;
// Write to DLC field in Master Control reg
p_CanMBoxes_->MBOX25.MSGCTRL.bit.DLC = 8;
p_CanMBoxes_->MBOX25.MSGCTRL.bit.RTR = 0;
//
// Configure Mailbox under test as a Receive mailbox
//
CanShadow_.CANMD.all = p_CanRegs_->CANMD.all;
CanShadow_.CANMD.bit.MD25 = 1;
p_CanRegs_->CANMD.all = CanShadow_.CANMD.all;
// Overwrite protection
// CanShadow_.CANOPC.all = p_CanRegs_->CANOPC.all;
// CanShadow_.CANOPC.bit.OPC1 = 1; // Should be one more mailbox to store 'overflow' messages
// p_CanRegs_->CANOPC.all = CanShadow_.CANOPC.all;
// Enable Mailbox
CanShadow_.CANME.all = p_CanRegs_->CANME.all;
CanShadow_.CANME.bit.ME25 = 1;
p_CanRegs_->CANME.all = CanShadow_.CANME.all;
// Write to the mailbox RAM field
p_CanMBoxes_->MBOX25.MDL.all = 0x55555555;
p_CanMBoxes_->MBOX25.MDH.all = 0x55555555;
} }
void CAN::transmitMsg(){ void CAN::transmitMsg(Uint16 boxNumber){
Uint32 mboxControl(0);
mboxControl = 1ul << boxNumber;
volatile struct MBOX* p_MailBox(NULL);
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
p_MailBox->MDH.all = 0x0;
p_MailBox->MDL.all = 0x0;
p_MailBox->MDH.all = 0xCCDD;
p_MailBox->MDL.all = 0xAABB;
CanShadow_.CANTRS.all = 0;
CanShadow_.CANTRS.all |= mboxControl; // Set TRS for mailbox under test
p_CanRegs_->CANTRS.all = CanShadow_.CANTRS.all;
do { CanShadow_.CANTA.all = p_CanRegs_->CANTA.all; }
while((CanShadow_.CANTA.all & mboxControl) == 0 );// Wait for TA1 bit to be set
CanShadow_.CANTA.all = 0;
CanShadow_.CANTA.all |= mboxControl; // Clear TA1
p_CanRegs_->CANTA.all = CanShadow_.CANTA.all;
} }
void CAN::receiveMsg(){ void CAN::receiveMsg(){

@ -15,11 +15,14 @@ public:
void initGpio(CAN_VARIANT canVarinat); void initGpio(CAN_VARIANT canVarinat);
void config(CAN_VARIANT canVarinat, Uint16 baudrate); void config(CAN_VARIANT canVarinat, Uint16 baudrate);
void configRxMBoxes();
void configTxMBoxes();
void transmitMsg(); void transmitMsg(Uint16 boxNumber);
void receiveMsg(); void receiveMsg();
private: private:
volatile struct ECAN_REGS* p_CanRegs_; volatile ECAN_REGS* p_CanRegs_;
volatile struct ECAN_MBOXES* p_CanMBoxes_; ECAN_REGS CanShadow_;
volatile ECAN_MBOXES* p_CanMBoxes_;
}; };

@ -5,9 +5,9 @@
#include <string.h> #include <string.h>
// #include "DSP2833x_ECan.h"
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File #include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "DSP2833x_Examples.h" #include "DSP2833x_Examples.h"
#include "SysConfig/f2833x_pinmux.h"
#include "Protocol/CAN.h" #include "Protocol/CAN.h"
@ -16,6 +16,10 @@ void idle_loop(void);
interrupt void cpu_timer0_isr(void); interrupt void cpu_timer0_isr(void);
//interrupt void adc_isr(void); //interrupt void adc_isr(void);
CAN canTest;
Uint16 msgsSent = 0;
Uint16 infCounter = 0;
volatile bool startTX = false;
void main() void main()
{ {
@ -73,8 +77,13 @@ void main()
// core.cpu_timers.start(); // core.cpu_timers.start();
// //
InitECanGpio(); canTest.initGpio(CANB);
InitECan(); canTest.config(CANB, 100);
canTest.configTxMBoxes();
canTest.configRxMBoxes();
// InitECanGpio();
// InitECan();
CpuTimer0.RegsAddr->TCR.bit.TSS = 0; CpuTimer0.RegsAddr->TCR.bit.TSS = 0;
@ -88,14 +97,12 @@ void idle_loop()
{ {
while (true) while (true)
{ {
/* infCounter++;
if (ECanaRegs.CANRMP.bit.RMP31) if (startTX){
{ startTX = false;
GpioDataRegs.GPADAT.bit.GPIO14 = 1;} canTest.transmitMsg(1);
else{ msgsSent++;
GpioDataRegs.GPADAT.bit.GPIO14 = 0;
} }
*/
}//end while }//end while

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