DVRLastVersionsCompare/SYSCTRL/HardWare.h

/*
 * HardWare.h
 *
 *      Author: Aleksey Gerasimenko
 *      gerasimenko.aleksey.n@gmail.com
 */

#include <math.h>
#include <stdint.h>

#include "framework.h"
#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h"


#ifndef SYSCTRL_HARDWARE_H_
#define SYSCTRL_HARDWARE_H_


namespace SYSCTRL
{


#define MASK_CELL_STATE_DOWN_COMM     (Uint16)0x0001
#define MASK_CELL_STATE_UP_COMM       (Uint16)0x0002
#define MASK_CELL_STATE_RESERVED_1    (Uint16)0x0004
#define MASK_CELL_STATE_RUNNING       (Uint16)0x0008
//
#define MASK_CELL_STATE_IGBT4_FAULT   (Uint16)0x0010
#define MASK_CELL_STATE_IGBT3_FAULT   (Uint16)0x0020
#define MASK_CELL_STATE_IGBT2_FAULT   (Uint16)0x0040
#define MASK_CELL_STATE_IGBT1_FAULT   (Uint16)0x0080
//
#define MASK_CELL_STATE_RESERVED_2    (Uint16)0x0100
#define MASK_CELL_STATE_TEMP_OVER     (Uint16)0x0200
#define MASK_CELL_STATE_UNDER_VOLTAGE (Uint16)0x0400
#define MASK_CELL_STATE_OVER_VOLTAGE  (Uint16)0x0800
//
#define MASK_CELL_STATE_RESERVED_3    (Uint16)0x0F800

#define MASK_CELL_STATE_FAULTS        (Uint16)(MASK_CELL_STATE_DOWN_COMM   |\
                                      MASK_CELL_STATE_UP_COMM     |\
                                      MASK_CELL_STATE_IGBT4_FAULT |\
                                      MASK_CELL_STATE_IGBT3_FAULT |\
                                      MASK_CELL_STATE_IGBT2_FAULT |\
                                      MASK_CELL_STATE_IGBT1_FAULT |\
                                      MASK_CELL_STATE_TEMP_OVER   |\
                                      MASK_CELL_STATE_UNDER_VOLTAGE |\
                                      MASK_CELL_STATE_OVER_VOLTAGE)

#define MASK_CELL_STATE_FAULTS_SHORT  (Uint16)(MASK_CELL_STATE_IGBT4_FAULT |\
                                      MASK_CELL_STATE_IGBT3_FAULT |\
                                      MASK_CELL_STATE_IGBT2_FAULT |\
                                      MASK_CELL_STATE_IGBT1_FAULT |\
                                      MASK_CELL_STATE_TEMP_OVER   |\
                                      MASK_CELL_STATE_OVER_VOLTAGE)

#define MASK_CELL_LOW_LEVEL           (Uint16)(MASK_CELL_STATE_DOWN_COMM |\
                                      MASK_CELL_STATE_UP_COMM |\
                                      MASK_CELL_STATE_UNDER_VOLTAGE)


struct HardWareVersion
{
    uint16_t      pwm;
    uint16_t      cell;
    uint32_t      cpu_cpld;
    HardWareVersion():
        pwm(uint16_t(0)),
        cell(uint16_t(0)),
        cpu_cpld(uint32_t(0))
    {}
};//HardWareVersion


struct HardWareConfiguration
{
    uint16_t      cell_level;
    //UnitSwitchingFreq switching_freq;
    SYSCTRL::HardWareVersion version;
    HardWareConfiguration():
        cell_level(0),
        //switching_freq(SWITCHING_FREQ_2500),
        version()
    {}
};//HardWareConfiguration


struct Cell
{
    CellState   state[3][13];
    float       dc_voltage[3][13];
    uint16_t      version[3][13];
    float       data_u;
    float       data_v;
    float       data_w;
    Cell():
        state(),
        dc_voltage(),
        version(),
        data_u(FP_ZERO),
        data_v(FP_ZERO),
        data_w(FP_ZERO)
    {}
};//Cell


struct HVCellDisableBit
{
    uint32_t cell_1: 1;
    uint32_t cell_2: 1;
    uint32_t cell_3: 1;
    uint32_t cell_4: 1;
    uint32_t cell_5: 1;
    uint32_t cell_6: 1;
    uint32_t cell_7: 1;
    uint32_t cell_8: 1;
    uint32_t cell_9: 1;
    uint32_t cell_10: 1;
    uint32_t cell_11: 1;
    uint32_t cell_12: 1;
    uint32_t cell_13: 1;
    uint32_t cell_14: 1;
    uint32_t cell_15: 1;
    uint32_t cell_16: 1;
    uint32_t cell_17: 1;
    uint32_t cell_18: 1;
};//HVCellDisableBit

union HVCellDisableRegister
{
    uint32_t all;
    HVCellDisableBit bits;
    HVCellDisableRegister():
        all((uint32_t)0)
    {}
};//HVCellDisableRegister

struct HardWareDisableBit
{
    uint16_t cpu_cpld: 1;
    uint16_t pwm_a: 1;
    uint16_t pwm_b: 1;
    uint16_t pwm_c: 1;
};//HardWareDisableBit

union HardWareDisableRegister
{
    uint16_t all;
    HardWareDisableBit bits;
    HardWareDisableRegister():
        all((uint16_t)0)
    {}
};//HardWareDisable


class HardWare
{
public:
    enum mode_fault_t {SHORT, COMPLETE};
public:
    bool enable;
    bool fault;
    bool fault_low_level;
    //UnitSwitchingFreq switching_freq;
    float dc_voltage_low_level;
    uint16_t      level;
    uint16_t      error;
    ControlOrder control_order_cell;
    ControlOrder ref_control_order;
    uint16_t      pwm_version[3];
    uint32_t      cpu_cpld_version;
    Cell        hvcell;
    HardWareDisableRegister disable_hw;
    HVCellDisableRegister disable_a_cells;
    HVCellDisableRegister disable_b_cells;
    HVCellDisableRegister disable_c_cells;
    HardWareVersion version_default;
public:
    HardWare();
    void configure(const HardWareConfiguration config);
    void check_status();
    void check_faults(mode_fault_t fmode);
    bool is_enable();
    bool is_fault();
    bool low_level();
    void reset();
    //
};//class HardWare


} /* namespace SYSCTRL */

#endif /* SYSCTRL_HARDWARE_H_ */