/*
 * HardWare.cpp
 *
 *      Author: Aleksey Gerasimenko
 *      gerasimenko.aleksey.n@gmail.com
 */

#include "SYSCTRL/HardWare.h"

namespace SYSCTRL
{
//CONSTRUCTOR
HardWare::HardWare():
        enable(true),
        fault(false),
        fault_low_level(false),
        level((Uint16)0),
        error((Uint16)0),
        //switching_freq(SWITCHING_FREQ_2500),
        dc_voltage_low_level(500.0),
        control_order_cell(ORDER_STOP),
        ref_control_order(ORDER_STOP),
        pwm_version(),
        cpu_cpld_version((Uint32)0),
        hvcell(),
        disable_hw(),
        disable_a_cells(),
        disable_b_cells(),
        disable_c_cells(),
        version_default()
{

    for(Uint16 phase = 0; phase < 3; phase++)
    {
        for(Uint16 cellnum = 0; cellnum < 13; cellnum++)
            {
                hvcell.dc_voltage[phase][cellnum] = FP_ZERO;
                hvcell.state[phase][cellnum].all = 0;
                hvcell.version[phase][cellnum] = 0;
                //
            }//for
        //
    }//for
    //
}//CONSTRUCTOR


void HardWare::configure(const HardWareConfiguration config)
{
    //switching_freq = config.switching_freq;
    level = config.cell_level;
    version_default = config.version;
    disable_hw.all = (uint16_t)0;
    disable_a_cells.all = (uint32_t)0;
    disable_b_cells.all = (uint32_t)0;
    disable_c_cells.all = (uint32_t)0;
    //
}//

#pragma CODE_SECTION("ramfuncs");
void HardWare::check_status()
{
    if(cpu_cpld_version != version_default.cpu_cpld)
    {
        disable_hw.bits.cpu_cpld = 1;
    }
    else
    {
        disable_hw.bits.cpu_cpld = 0;
        //
    }//if else
    //
    if(pwm_version[0] != version_default.pwm)
    {
        disable_hw.bits.pwm_a = 1;
    }
    else
    {
        disable_hw.bits.pwm_a = 0;
        //
    }//if else
    //
    if(pwm_version[1] != version_default.pwm)
    {
        disable_hw.bits.pwm_b = 1;
    }
    else
    {
        disable_hw.bits.pwm_b = 0;
        //
    }//if else
    //
    if(pwm_version[2] != version_default.pwm)
    {
        disable_hw.bits.pwm_c = 1;
    }
    else
    {
        disable_hw.bits.pwm_c = 0;
        //
    }//if else

    static uint32_t mask = (uint32_t)0;
    static uint32_t auxreg_0 = (uint32_t)0;
    static uint32_t auxreg_1 = (uint32_t)0;
    static uint32_t auxreg_2 = (uint32_t)0;
    auxreg_0 = (uint32_t)0;
    auxreg_1 = (uint32_t)0;
    auxreg_2 = (uint32_t)0;
    for(Uint16 cellnum = 0; cellnum < level; cellnum++)
    {
        mask = (uint32_t)0;
        if(hvcell.version[0][cellnum] != version_default.cell)
        {
            mask = (uint32_t)0;
            mask = 1 << (cellnum);
            auxreg_0 |= mask;
        }
        else
        {
            mask = (uint32_t)0;
            mask = 1 << (cellnum);
            mask = (uint32_t)((uint32_t)0xFFFFFFFF ^ (uint32_t)mask);
            auxreg_0 &= mask;
            //
        }//if
        //
        mask = (uint32_t)0;
        if(hvcell.version[1][cellnum] != version_default.cell)
        {
            mask = 1 << (cellnum);
            auxreg_1 |= mask;
        }
        else
        {
            mask = 1 << (cellnum);
            mask = (uint32_t)((uint32_t)0xFFFFFFFF ^ (uint32_t)mask);
            auxreg_1 &= mask;
            //
        }//if
        //
        mask = (uint32_t)0;
        if(hvcell.version[2][cellnum] != version_default.cell)
        {
            mask = 1 << (cellnum);
            auxreg_2 |= mask;
        }
        else
        {
            mask = 1 << (cellnum);
            mask = (uint32_t)((uint32_t)0xFFFFFFFF ^ (uint32_t)mask);
            auxreg_2 &= mask;
            //
        }//if
        //
    }//for
    //
    disable_a_cells.all = (uint32_t)auxreg_0;
    disable_c_cells.all = (uint32_t)auxreg_1;
    disable_b_cells.all = (uint32_t)auxreg_2;
    //
    static bool tmp_enable = true;
    tmp_enable = true;
//    tmp_enable &= disable_hw.all == 0 ? true : false;
//    tmp_enable &= disable_a_cells.all == 0 ? true : false;
//    tmp_enable &= disable_b_cells.all == 0 ? true : false;
//    tmp_enable &= disable_c_cells.all == 0 ? true : false;
    enable = tmp_enable;
    //
}//
//
#pragma CODE_SECTION("ramfuncs");
bool HardWare::is_enable()
{
    //
    return enable;
    //
}//
#pragma CODE_SECTION("ramfuncs");
void HardWare::check_faults(mode_fault_t fmode)
{

    for(Uint16 cellnum = 0; cellnum < level; cellnum++)
    {
        for(Uint16 phasenum = 0; phasenum < 3; phasenum++)
        {

            if(SYSCTRL::HardWare::COMPLETE == fmode)
            {
                if(((Uint16)(MASK_CELL_STATE_FAULTS & hvcell.state[phasenum][cellnum].all)) != (Uint16)0)
                {
                    fault = true;
                    //
                }//
            }
            else
            {
                if(((Uint16)(MASK_CELL_STATE_FAULTS_SHORT & hvcell.state[phasenum][cellnum].all)) != (Uint16)0)
                {
                    fault = true;
                    //
                }//
            }

            if(((Uint16)(MASK_CELL_LOW_LEVEL & hvcell.state[phasenum][cellnum].all)) != (Uint16)0)
            {
                fault_low_level = true;
            }

            //
        };//for
        //
    }//for
    //
}//
#pragma CODE_SECTION("ramfuncs");
bool HardWare::is_fault()
{
    return fault;
    //
}//
//
#pragma CODE_SECTION("ramfuncs");
bool HardWare::low_level()
{
    return fault_low_level;
    //
}//

#pragma CODE_SECTION("ramfuncs");
void HardWare::reset()
{
    fault = false;
    fault_low_level = false;
    //
}//
//
} /* namespace SYSCTRL */