CCS-COMM_BOARD/Protocol/CAN.cpp

#include "CAN.h"

CAN::CAN(){

}

void CAN::initGpio(CAN_VARIANT canVarinat){
    if(canVarinat == CAN_VARIAN::CANA) InitECanaGpio();
    else if (canVarinat == CAN_VARIAN::CANB) InitECanbGpio();
}

void CAN::config(CAN_VARIANT canVarinat, Uint16 baudrate){
    if (CAN == CANA){
		EALLOW;
		SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1;
		EDIS;
		p_CanRegs_ = &ECanaRegs;
		p_CanMBoxes_ = &ECanaMboxes;
	}
	else if (CAN == CANB){
		EALLOW;
		SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1;
		EDIS;
		p_CanRegs_ = &ECanbRegs;
		p_CanMBoxes_ = &ECanbMboxes;
	}
	else { return; }

    //
    // Create a shadow register structure for the CAN control registers. This 
    // is needed, since only 32-bit access is allowed to these registers. 
    // 16-bit access to these registers could potentially corrupt the register
    // contents or return false data. This is especially true while writing 
    // to/reading from a bit (or group of bits) among bits 16 - 31
    //
    struct ECAN_REGS ECanShadow;

    EALLOW;		// EALLOW enables access to protected bits

    //
    // Configure eCAN RX and TX pins for CAN operation using eCAN regs
    //
    ECanShadow.CANTIOC.all = p_CanRegs_.CANTIOC.all;
    ECanShadow.CANTIOC.bit.TXFUNC = 1;
    p_CanRegs_.CANTIOC.all = ECanShadow.CANTIOC.all;

    ECanShadow.CANRIOC.all = p_CanRegs_.CANRIOC.all;
    ECanShadow.CANRIOC.bit.RXFUNC = 1;
    p_CanRegs_.CANRIOC.all = ECanShadow.CANRIOC.all;

    //
    // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
    // HECC mode also enables time-stamping feature
    //
    ECanShadow.CANMC.all = p_CanRegs_.CANMC.all;
    ECanShadow.CANMC.bit.SCB = 1;
    p_CanRegs_.CANMC.all = ECanShadow.CANMC.all;

    //
    // Initialize all bits of 'Master Control Field' to zero
    // Some bits of MSGCTRL register come up in an unknown state. For proper 
    // operation, all bits (including reserved bits) of MSGCTRL must be 
    // initialized to zero
    //
    p_CanMBoxes_.MBOX0.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX1.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX2.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX3.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX4.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX5.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX6.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX7.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX8.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX9.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX10.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX11.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX12.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX13.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX14.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX15.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX16.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX17.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX18.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX19.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX20.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX21.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX22.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX23.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX24.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX25.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX26.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX27.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX28.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX29.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX30.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_.MBOX31.MSGCTRL.all = 0x00000000;

    //
    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution.
    //
    p_CanRegs_.CANTA.all	= 0xFFFFFFFF;       // Clear all TAn bits

    p_CanRegs_.CANRMP.all = 0xFFFFFFFF;      // Clear all RMPn bits

    p_CanRegs_.CANGIF0.all = 0xFFFFFFFF;     // Clear all interrupt flag bits
    p_CanRegs_.CANGIF1.all = 0xFFFFFFFF;

    //
    // Configure bit timing parameters for eCANA
    //
    ECanShadow.CANMC.all = p_CanRegs_.CANMC.all;
    ECanShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    p_CanRegs_.CANMC.all = ECanShadow.CANMC.all;

    ECanShadow.CANES.all = p_CanRegs_.CANES.all;

    do
    {
        ECanShadow.CANES.all = p_CanRegs_.CANES.all;
    } while(ECanShadow.CANES.bit.CCE != 1 );  	// Wait for CCE bit to be set

    ECanShadow.CANBTC.all = 0;

    // The following block for all 150 MHz SYSCLKOUT 
    // (75 MHz CAN clock) - default. Bit rate = 1 Mbps
    //
    
    switch (baudrate) {
        case : 1000
        ECanShadow.CANBTC.bit.BRPREG = 4;
        ECanShadow.CANBTC.bit.TSEG2REG = 3;
        ECanShadow.CANBTC.bit.TSEG1REG = 9;
        break;

        case : 500
        ECanShadow.CANBTC.bit.BRPREG = 9;
        ECanShadow.CANBTC.bit.TSEG2REG = 3;
        ECanShadow.CANBTC.bit.TSEG1REG = 9;
        break;

        case : 250
        ECanShadow.CANBTC.bit.BRPREG = 19;
        ECanShadow.CANBTC.bit.TSEG2REG = 3;
        ECanShadow.CANBTC.bit.TSEG1REG = 9;
        break;

        case : 100
        ECanShadow.CANBTC.bit.BRPREG = 49;
        ECanShadow.CANBTC.bit.TSEG2REG = 3;
        ECanShadow.CANBTC.bit.TSEG1REG = 9;
        break;

        default: return;
    }

    ECanShadow.CANBTC.bit.SAM = 1;
    p_CanRegs_.CANBTC.all = ECanShadow.CANBTC.all;

    ECanShadow.CANMC.all = p_CanRegs_.CANMC.all;
    ECanShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    p_CanRegs_.CANMC.all = ECanShadow.CANMC.all;

    ECanShadow.CANES.all = p_CanRegs_.CANES.all;

    do
    {
        ECanShadow.CANES.all = p_CanRegs_.CANES.all;
    } while(ECanShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be  cleared

    //
    // Disable all Mailboxes
    //
    p_CanRegs_.CANME.all = 0;		// Required before writing the MSGIDs

    EDIS;



}

void CAN::transmitMsg(){

}

void CAN::receiveMsg(){

}