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CCS-COMM_BOARD/PERIPHERY/PWMABCInterace.cpp

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/*
* PWMInterace.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMABCInterace.h"
namespace PERIPHERY
{
//CONSTRUCTOR
PWMABCInterace::PWMABCInterace():
PWMInterface(),
m_counter_phase(0),
m_telemetry_phase_counter(0),
m_telemetry_phase_quantity(3),
m_phase(),
_telemetry_execute(&PWMABCInterace::_telemetry_sequence_one)
//
{}//CONSTRUCTOR
//
void PWMABCInterace::setup(uint16_t *memzone)
{
_setup_phase(m_phase[0], memzone + OFFSET_PWM_PHASE_A);
_setup_phase(m_phase[1], memzone + OFFSET_PWM_PHASE_B);
_setup_phase(m_phase[2], memzone + OFFSET_PWM_PHASE_C);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = &DSP28335::GPIO::gpio_hard_fault_setup;
_hard_fault_read = &DSP28335::GPIO::gpio_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMABCInterace::setup(const PWMStructureSetup& setup)
{
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMABCInterace::setup(uint16_t *memzone, const PWMStructureSetup& setup)
{
_setup_phase(m_phase[0], memzone + OFFSET_PWM_PHASE_A);
_setup_phase(m_phase[1], memzone + OFFSET_PWM_PHASE_B);
_setup_phase(m_phase[2], memzone + OFFSET_PWM_PHASE_C);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::initialization(PWMABCInterfaceConfiguration& config)
{
//set_frequency((uint16_t)config.pwm_frequency);
set_cell_quantity_phase(config.cell_quantity[0], config.cell_quantity[1], config.cell_quantity[2]);
set_cmp(0, 0, 0);
set_order(0);
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_setup_phase(PWMPhaseStructure& phase, uint16_t *base)
{
phase.p_pwm_frequency = base + OFFSET_FREQ_PWM;
phase.p_cell_quantity_in_phase = base + OFFSET_CQ_IN_PHASE;
phase.p_compare = base + OFFSET_CMP;
phase.p_order = base + OFFSET_ORDER;
phase.p_pwm_state = base + OFFSET_PWM_STATE;
phase.p_pwm_version = base + OFFSET_PWM_VERSION;
phase.a_cell_quantity_in_cascade[0] = base + OFFSET_CQ_IN_CASC_00;
phase.a_cell_quantity_in_cascade[1] = base + OFFSET_CQ_IN_CASC_01;
phase.a_cell_quantity_in_cascade[2] = base + OFFSET_CQ_IN_CASC_02;
phase.a_cell_quantity_in_cascade[3] = base + OFFSET_CQ_IN_CASC_03;
phase.a_cell_quantity_in_cascade[4] = base + OFFSET_CQ_IN_CASC_04;
phase.a_cell_quantity_in_cascade[5] = base + OFFSET_CQ_IN_CASC_05;
phase.a_cell_quantity_in_cascade[6] = base + OFFSET_CQ_IN_CASC_06;
phase.a_cell_quantity_in_cascade[7] = base + OFFSET_CQ_IN_CASC_07;
phase.a_cell_quantity_in_cascade[8] = base + OFFSET_CQ_IN_CASC_08;
phase.a_cell_quantity_in_cascade[9] = base + OFFSET_CQ_IN_CASC_09;
phase.a_cell_quantity_in_cascade[10] = base + OFFSET_CQ_IN_CASC_10;
phase.a_cell_quantity_in_cascade[11] = base + OFFSET_CQ_IN_CASC_11;
phase.a_cell_quantity_in_cascade[12] = base + OFFSET_CQ_IN_CASC_12;
phase.a_cell_quantity_in_cascade[13] = base + OFFSET_CQ_IN_CASC_13;
phase.a_cell_quantity_in_cascade[14] = base + OFFSET_CQ_IN_CASC_14;
phase.a_cell_quantity_in_cascade[15] = base + OFFSET_CQ_IN_CASC_15;
phase.a_cell_quantity_in_cascade[16] = base + OFFSET_CQ_IN_CASC_16;
phase.a_cell_quantity_in_cascade[17] = base + OFFSET_CQ_IN_CASC_17;
phase.p_telemetry_box = base + OFFSET_TELEMETRY;
phase.p_breakdown_cell_state = base + OFFSET_CELL_BREAKDOWN;
phase.p_breakdown_cell_address = base + OFFSET_CELL_BREAKDOWN_ADR;
phase.a_cascade_pointers[0] = base + OFFSET_CASCADE_00;
phase.a_cascade_pointers[1] = base + OFFSET_CASCADE_01;
phase.a_cascade_pointers[2] = base + OFFSET_CASCADE_02;
phase.a_cascade_pointers[3] = base + OFFSET_CASCADE_03;
phase.a_cascade_pointers[4] = base + OFFSET_CASCADE_04;
phase.a_cascade_pointers[5] = base + OFFSET_CASCADE_05;
phase.a_cascade_pointers[6] = base + OFFSET_CASCADE_06;
phase.a_cascade_pointers[7] = base + OFFSET_CASCADE_07;
phase.a_cascade_pointers[8] = base + OFFSET_CASCADE_08;
phase.a_cascade_pointers[9] = base + OFFSET_CASCADE_09;
phase.a_cascade_pointers[10] = base + OFFSET_CASCADE_10;
phase.a_cascade_pointers[11] = base + OFFSET_CASCADE_11;
phase.a_cascade_pointers[12] = base + OFFSET_CASCADE_12;
phase.a_cascade_pointers[13] = base + OFFSET_CASCADE_13;
phase.a_cascade_pointers[14] = base + OFFSET_CASCADE_14;
phase.a_cascade_pointers[15] = base + OFFSET_CASCADE_15;
phase.a_cascade_pointers[16] = base + OFFSET_CASCADE_16;
phase.a_cascade_pointers[17] = base + OFFSET_CASCADE_17;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_frequency(uint16_t freq)
{
NOP;
NOP;
NOP;
*m_phase[0].p_pwm_frequency = freq;
*m_phase[1].p_pwm_frequency = freq;
*m_phase[2].p_pwm_frequency = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cascade_quantity()
{
//m_config.cascade_quantity[0] = quant_a;
//m_config.cascade_quantity[1] = quant_b;
//m_config.cascade_quantity[2] = quant_c;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cell_quantity_phase(uint16_t quant_a, uint16_t quant_b, uint16_t quant_c)
{
// m_config.cell_quantity[0]= quant_a;
// m_config.cell_quantity[1]= quant_b;
// m_config.cell_quantity[2]= quant_c;
NOP;
NOP;
NOP;
*m_phase[0].p_cell_quantity_in_phase = quant_a;
*m_phase[1].p_cell_quantity_in_phase = quant_b;
*m_phase[2].p_cell_quantity_in_phase = quant_c;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cmp(uint16_t cmpra, uint16_t cmprb, uint16_t cmprc)
{
NOP;
NOP;
NOP;
*m_phase[0].p_compare = cmpra;
*m_phase[1].p_compare = cmprb;
*m_phase[2].p_compare = cmprc;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_phase[0].p_order = order;
*m_phase[1].p_order = order;
*m_phase[2].p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_board_state(uint16_t& state_pwm_a, uint16_t& state_pwm_b, uint16_t& state_pwm_c)
{
NOP;
NOP;
NOP;
state_pwm_a = *m_phase[0].p_pwm_state;
state_pwm_b = *m_phase[1].p_pwm_state;
state_pwm_c = *m_phase[2].p_pwm_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_sw_version(uint16_t& version_pwm_a, uint16_t& version_pwm_b, uint16_t& version_pwm_c)
{
NOP;
NOP;
NOP;
version_pwm_a = *m_phase[0].p_pwm_version;
version_pwm_b = *m_phase[1].p_pwm_version;
version_pwm_c = *m_phase[2].p_pwm_version;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_breakdown_cell_state(uint16_t& cellstate_pwm_a, uint16_t& cellstate_pwm_b, uint16_t& cellstate_pwm_c)
{
NOP;
NOP;
NOP;
cellstate_pwm_a = *m_phase[0].p_breakdown_cell_state;
cellstate_pwm_b = *m_phase[1].p_breakdown_cell_state;
cellstate_pwm_c = *m_phase[2].p_breakdown_cell_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_breakdown_cell_index(uint16_t& cellindex_pwm_a, uint16_t& cellindex_pwm_b, uint16_t& cellindex_pwm_c)
{
NOP;
NOP;
NOP;
cellindex_pwm_a = *m_phase[0].p_breakdown_cell_address;
cellindex_pwm_b = *m_phase[1].p_breakdown_cell_address;
cellindex_pwm_c = *m_phase[2].p_breakdown_cell_address;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cell_quantity_cascade(uint16_t phase_index, uint16_t cascadenum, uint16_t quant)
{
// m_config.cell_quantity_in_cascade[phase_index][cascadenum] = quant;
NOP;
NOP;
NOP;
*m_phase[phase_index].a_cell_quantity_in_cascade[cascadenum] = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_broadcast.p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_cell_quantity_phase(uint16_t quant)
{
// m_config.cell_quantity[0]= quant;
// m_config.cell_quantity[1]= quant;
// m_config.cell_quantity[2]= quant;
NOP;
NOP;
NOP;
*m_broadcast.p_cell_quantity_in_phase = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_freq(uint16_t freq)
{
// m_config.pwm_frequency = freq;
NOP;
NOP;
NOP;
*m_broadcast.p_freq = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_hard_fault(uint16_t& hard_fault)
{
(*_hard_fault_read)(m_hard_fault.all);
hard_fault = m_hard_fault.all;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_indirect_access(uint16_t phase, uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry)
{
m_aux_pointer = m_phase[phase].a_cascade_pointers[cascade] + m_offset_cells.cell_offset[cell];
NOP;
NOP;
NOP;
*m_phase[phase].p_telemetry_box = offset;
telemetry = *m_aux_pointer;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::telemetry_execute(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
(this->*_telemetry_execute)(config, telemetry_phase);
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::reset_telemetry()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_telemetry_sequence_one()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMABCInterace::_telemetry_sequence_one;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_telemetry_sequence_two()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMABCInterace::_telemetry_sequence_two;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_telemetry_sequence_one(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
//
m_telemetry_function_quantity = 11;
m_telemetry_cascade_quantity = config.cascade_quantity[m_telemetry_phase_counter];
m_telemetry_cell_quantity = config.cell_quantity_in_cascade[m_telemetry_phase_counter][m_telemetry_cascade_counter];
//
switch(m_telemetry_function_counter)
{
case 0:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.state, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].state);
break;
}
case 1:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.saw_init_val, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].saw_init_val);
break;
}
case 2:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.version, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].version);
break;
}
case 3:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_pcb, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_pcb);
break;
}
case 4:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.ctrl_faults, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].ctrl_faults);
break;
}
case 5:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_l, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_l);
break;
}
case 6:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.voltage, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].voltage);
break;
}
case 7:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.freq_pwm, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].freq_pwm);
break;
}
case 8:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.time_cntr, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].time_cntr);
break;
}
case 9:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_rad, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_rad);
break;
}
case 10:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.sync_faults, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].sync_faults);
break;
}
case 11:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_h, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_h);
break;
}
default:{}
}//switch
m_telemetry_cell_counter++;
if(m_telemetry_cell_counter >= m_telemetry_cell_quantity)
{
m_telemetry_cell_counter = 0;
m_telemetry_cascade_counter++;
if(m_telemetry_cascade_counter >= m_telemetry_cascade_quantity)
{
m_telemetry_cascade_counter = 0;
m_telemetry_function_counter++;
if(m_telemetry_function_counter > m_telemetry_function_quantity)
{
m_telemetry_function_counter = 0;
m_telemetry_phase_counter++;
if(m_telemetry_phase_counter >= m_telemetry_phase_quantity)
{
m_telemetry_phase_counter = 0;
//
}//if
}//if
//
}//if
//
}//if
//
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_telemetry_sequence_two(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
//
}//
//
//
} /* namespace PERIPHERAL */
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