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#include "CAN.h"
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namespace canSpace {
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CAN::CAN(CAN_VARIANT canVariant) :
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canPort(canVariant)
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{}
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void CAN::initGpio(){
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if(canPort == CANA) InitECanaGpio();
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else if (canPort == CANB) InitECanbGpio();
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}
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void CAN::config(Uint16 baudrate, Uint16 flags){
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if (canPort == CANA){
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1;
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EDIS;
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p_CanRegs_ = &ECanaRegs;
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p_CanMBoxes_ = &ECanaMboxes;
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}
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else if (canPort == CANB){
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1;
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EDIS;
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p_CanRegs_ = &ECanbRegs;
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p_CanMBoxes_ = &ECanbMboxes;
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}
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else { return; }
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// Create a shadow register structure for the CAN control registers. This // TODO add this into description
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// is needed, since only 32-bit access is allowed to these registers.
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// 16-bit access to these registers could potentially corrupt the register
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// contents or return false data. This is especially true while writing
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// to/reading from a bit (or group of bits) among bits 16 - 31
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EALLOW;
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// Configure eCAN RX and TX pins for CAN operation using eCAN regs
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CanShadow_.CANTIOC.all = p_CanRegs_->CANTIOC.all;
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CanShadow_.CANTIOC.bit.TXFUNC = 1;
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p_CanRegs_->CANTIOC.all = CanShadow_.CANTIOC.all;
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CanShadow_.CANRIOC.all = p_CanRegs_->CANRIOC.all;
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CanShadow_.CANRIOC.bit.RXFUNC = 1;
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p_CanRegs_->CANRIOC.all = CanShadow_.CANRIOC.all;
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// Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
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// HECC mode also enables time-stamping feature
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CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
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CanShadow_.CANMC.bit.SCB = 1;
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p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
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// Initialize all bits of 'Master Control Field' to zero
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// Some bits of MSGCTRL register come up in an unknown state. For proper
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// operation, all bits (including reserved bits) of MSGCTRL must be
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// initialized to zero
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p_CanMBoxes_->MBOX0.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX1.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX2.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX3.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX4.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX5.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX6.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX7.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX8.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX9.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX10.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX11.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX12.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX13.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX14.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX15.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX16.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX17.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX18.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX19.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX20.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX21.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX22.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX23.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX24.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX25.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX26.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX27.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX28.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX29.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX30.MSGCTRL.all = 0x00000000;
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p_CanMBoxes_->MBOX31.MSGCTRL.all = 0x00000000;
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// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
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// as a matter of precaution.
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p_CanRegs_->CANTA.all = 0xFFFFFFFF;
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p_CanRegs_->CANRMP.all = 0xFFFFFFFF;
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p_CanRegs_->CANGIF0.all = 0xFFFFFFFF;
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p_CanRegs_->CANGIF1.all = 0xFFFFFFFF;
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// Configure bit timing parameters for eCANA
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CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
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CanShadow_.CANMC.bit.CCR = 1 ;
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p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
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do { CanShadow_.CANES.all = p_CanRegs_->CANES.all; }
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while(CanShadow_.CANES.bit.CCE != 1 );
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// MSB - 0; LSB - 1
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CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
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if (flags & MSB_ENABLE){
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CanShadow_.CANMC.bit.DBO = 0;
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}
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else
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{ CanShadow_.CANMC.bit.DBO = 1; }
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p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
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CanShadow_.CANBTC.all = 0;
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// The following block for all 150 MHz SYSCLKOUT
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// (75 MHz CAN clock) - default. Bit rate = 1 Mbps / 500 kbps / 250 kbps / 100 kbps
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switch (baudrate) {
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case 1000:
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CanShadow_.CANBTC.bit.BRPREG = 4;
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CanShadow_.CANBTC.bit.TSEG2REG = 3;
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CanShadow_.CANBTC.bit.TSEG1REG = 9;
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break;
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case 500:
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CanShadow_.CANBTC.bit.BRPREG = 9;
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CanShadow_.CANBTC.bit.TSEG2REG = 3;
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CanShadow_.CANBTC.bit.TSEG1REG = 9;
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break;
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case 250:
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CanShadow_.CANBTC.bit.BRPREG = 19;
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CanShadow_.CANBTC.bit.TSEG2REG = 3;
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CanShadow_.CANBTC.bit.TSEG1REG = 9;
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break;
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case 100:
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CanShadow_.CANBTC.bit.BRPREG = 49;
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CanShadow_.CANBTC.bit.TSEG2REG = 3;
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CanShadow_.CANBTC.bit.TSEG1REG = 9;
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break;
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default: return;
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}
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CanShadow_.CANBTC.bit.SAM = 1;
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p_CanRegs_->CANBTC.all = CanShadow_.CANBTC.all;
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CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
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CanShadow_.CANMC.bit.CCR = 0 ;
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p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
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do { CanShadow_.CANES.all = p_CanRegs_->CANES.all; }
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while(CanShadow_.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared
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// Disable all Mailboxes
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p_CanRegs_->CANME.all = 0;
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// Disable all interrupts
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p_CanRegs_->CANGIM.all = 0;
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p_CanRegs_->CANMIM.all = 0;
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//
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// Debug feature
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// Configure the eCAN for self test mode.
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CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
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if (flags & STM_ENABLE){
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CanShadow_.CANMC.bit.STM = 1;
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}
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else
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{ CanShadow_.CANMC.bit.STM = 0; }
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p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
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EDIS;
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}
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void CAN::configTxMBox(Uint16 boxNumber, const MsgID& configID, const MsgCtrlReg& configCtrlReg){
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if (boxNumber > 31) return;
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volatile MBOX* p_MailBox(0);
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p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
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Uint32 mboxControl(0);
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mboxControl = 1ul << boxNumber;
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// Reset transmittion
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if (CanShadow_.CANTRS.all &= mboxControl)
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{
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CanShadow_.CANTRR.all = p_CanRegs_->CANTRR.all;
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CanShadow_.CANTRR.all |= mboxControl;
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p_CanRegs_->CANTRR.all = CanShadow_.CANTRR.all;
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do {CanShadow_.CANTRS.all = p_CanRegs_->CANTRS.all;}
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while((CanShadow_.CANTRS.all & mboxControl) != 0); // Wait for TRS bit to be cleared
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}
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// Mailbox disable
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CanShadow_.CANME.all = p_CanRegs_->CANME.all;
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CanShadow_.CANME.all &= ~(mboxControl);
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p_CanRegs_->CANME.all = CanShadow_.CANME.all;
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// Write to the MSGID field
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p_MailBox->MSGID.all = configID.all;
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// Mailbox direction - transmit
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CanShadow_.CANMD.all = p_CanRegs_->CANMD.all;
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CanShadow_.CANMD.all &= ~(mboxControl);
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p_CanRegs_->CANMD.all = CanShadow_.CANMD.all;
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// Config MBOX control reg
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p_MailBox->MSGCTRL.all = configCtrlReg.all;
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// Mailbox enable
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CanShadow_.CANME.all = p_CanRegs_->CANME.all;
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CanShadow_.CANME.all |= mboxControl;
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p_CanRegs_->CANME.all = CanShadow_.CANME.all;
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}
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void CAN::configRxMBox(Uint16 boxNumber, const MsgID& configID, const MsgCtrlReg& configCtrlReg){
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if (boxNumber > 31) return;
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volatile MBOX* p_MailBox(0);
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p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
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Uint32 mboxControl(0);
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mboxControl = 1ul << boxNumber;
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// Mailbox disable
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CanShadow_.CANME.all = p_CanRegs_->CANME.all;
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CanShadow_.CANME.all &= ~(mboxControl);
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p_CanRegs_->CANME.all = CanShadow_.CANME.all;
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// Write to the MSGID field
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p_MailBox->MSGID.all = 0x0;
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p_MailBox->MSGID.all = configID.all;
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// Write to DLC and RTR field in control reg
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p_MailBox->MSGCTRL.bit.DLC = configCtrlReg.bit.DLC;
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p_MailBox->MSGCTRL.bit.RTR = configCtrlReg.bit.RTR;
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// Configure Mailbox under test as a Receive mailbox
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CanShadow_.CANMD.all = p_CanRegs_->CANMD.all;
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CanShadow_.CANMD.all |= mboxControl;
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p_CanRegs_->CANMD.all = CanShadow_.CANMD.all;
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// Overwrite protection
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// If "ON" make sure that an additional mailbox is configured to store ’overflow’ messages.
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if(configCtrlReg.bit.OPC){
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CanShadow_.CANOPC.all = p_CanRegs_->CANOPC.all;
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CanShadow_.CANOPC.all |= mboxControl;
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p_CanRegs_->CANOPC.all = CanShadow_.CANOPC.all;
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}
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// Enable Mailbox
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CanShadow_.CANME.all = p_CanRegs_->CANME.all;
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CanShadow_.CANME.all |= mboxControl;
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p_CanRegs_->CANME.all = CanShadow_.CANME.all;
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}
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void CAN::configSystemIsr(Uint32 flags){
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EALLOW;
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p_CanRegs_->CANGIM.all = flags;
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EDIS;
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}
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void CAN::configMBoxIsr(Uint16 boxNumber){
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if (boxNumber > 31) return;
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Uint32 mboxControl(0);
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mboxControl = 1ul << boxNumber;
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EALLOW;
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p_CanRegs_->CANMIL.all |= mboxControl;
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p_CanRegs_->CANMIM.all |= mboxControl;
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EDIS;
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}
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} //canSpace
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