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304 lines
9.3 KiB
C
304 lines
9.3 KiB
C
//###########################################################################
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//
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// FILE: DSP2833x_Xintf.c
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//
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// TITLE: DSP2833x Device External Interface Init & Support Functions.
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//
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// DESCRIPTION:
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//
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// Example initialization function for the external interface (XINTF).
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// This example configures the XINTF to its default state. For an
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// example of how this function being used refer to the
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// examples/run_from_xintf project.
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//
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//###########################################################################
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// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
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// $Release Date: November 1, 2016 $
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// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
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// http://www.ti.com/ ALL RIGHTS RESERVED $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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//
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// InitXINTF - This function initializes the External Interface the default
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// reset state.
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//
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// Do not modify the timings of the XINTF while running from the XINTF. Doing
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// so can yield unpredictable results
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//
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void
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InitXintf(void)
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{
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//
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// This shows how to write to the XINTF registers. The
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// values used here are the default state after reset.
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// Different hardware will require a different configuration.
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//
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//
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// For an example of an XINTF configuration used with the
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// F28335 eZdsp, refer to the examples/run_from_xintf project.
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//
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//
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// Any changes to XINTF timing should only be made by code
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// running outside of the XINTF.
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//
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//
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// All Zones
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// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
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//
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EALLOW;
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XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
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//
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// No write buffering
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//
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XintfRegs.XINTCNF2.bit.WRBUFF = 0;
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//
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// XCLKOUT is enabled
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//
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XintfRegs.XINTCNF2.bit.CLKOFF = 0;
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//
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// XCLKOUT = XTIMCLK/2
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//
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XintfRegs.XINTCNF2.bit.CLKMODE = 1;
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//
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// Zone 0
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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//
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XintfRegs.XTIMING0.bit.XWRLEAD = 3;
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XintfRegs.XTIMING0.bit.XWRACTIVE = 5;
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XintfRegs.XTIMING0.bit.XWRTRAIL = 1;
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//
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// Zone read timing
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//
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XintfRegs.XTIMING0.bit.XRDLEAD = 3;
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XintfRegs.XTIMING0.bit.XRDACTIVE = 5;
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XintfRegs.XTIMING0.bit.XRDTRAIL = 1;
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//
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// double all Zone read/write lead/active/trail timing
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//
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XintfRegs.XTIMING0.bit.X2TIMING = 1;
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//
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// Zone will sample XREADY signal
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//
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XintfRegs.XTIMING0.bit.USEREADY = 1;
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XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
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//
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// Size must be either:
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// 0,1 = x32 or
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// 1,1 = x16 other values are reserved
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//
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XintfRegs.XTIMING0.bit.XSIZE = 3;
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//
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// Zone 6
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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//
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XintfRegs.XTIMING6.bit.XWRLEAD = 3;
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XintfRegs.XTIMING6.bit.XWRACTIVE = 5;
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XintfRegs.XTIMING6.bit.XWRTRAIL = 1;
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//
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// Zone read timing
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//
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XintfRegs.XTIMING6.bit.XRDLEAD = 3;
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XintfRegs.XTIMING6.bit.XRDACTIVE = 5;
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XintfRegs.XTIMING6.bit.XRDTRAIL = 1;
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//
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// double all Zone read/write lead/active/trail timing
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//
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XintfRegs.XTIMING6.bit.X2TIMING = 1;
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//
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// Zone will sample XREADY signal
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//
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XintfRegs.XTIMING6.bit.USEREADY = 0;
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XintfRegs.XTIMING6.bit.READYMODE = 0; // sample asynchronous
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//
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// Size must be either:
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// 0,1 = x32 or
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// 1,1 = x16 other values are reserved
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//
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XintfRegs.XTIMING6.bit.XSIZE = 3;
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//
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// Zone 7
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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//
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XintfRegs.XTIMING7.bit.XWRLEAD = 3;
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XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
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XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
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//
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// Zone read timing
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//
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XintfRegs.XTIMING7.bit.XRDLEAD = 3;
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XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
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XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
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//
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// double all Zone read/write lead/active/trail timing
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//
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XintfRegs.XTIMING7.bit.X2TIMING = 1;
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//
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// Zone will sample XREADY signal
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//
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XintfRegs.XTIMING7.bit.USEREADY = 1;
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XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
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//
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// Size must be either:
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// 0,1 = x32 or
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// 1,1 = x16 other values are reserved
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//
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XintfRegs.XTIMING7.bit.XSIZE = 3;
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//
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// Bank switching
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// Assume Zone 7 is slow, so add additional BCYC cycles
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// when ever switching from Zone 7 to another Zone.
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// This will help avoid bus contention.
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//
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XintfRegs.XBANK.bit.BANK = 7;
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XintfRegs.XBANK.bit.BCYC = 7;
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EDIS;
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//
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// Force a pipeline flush to ensure that the write to the last register
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// configured occurs before returning.
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//
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InitXintf16Gpio();
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//InitXintf32Gpio();
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asm(" RPT #7 || NOP");
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}
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//
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// InitXintf32Gpio -
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//
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void
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InitXintf32Gpio()
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{
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EALLOW;
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GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
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GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
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GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
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GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
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GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
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GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
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GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
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GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
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GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
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GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
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GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
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GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
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GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
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GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
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GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
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GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
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GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
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GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
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InitXintf16Gpio();
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}
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//
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// InitXintf16Gpio -
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//
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void
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InitXintf16Gpio()
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{
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EALLOW;
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GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
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GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
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GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
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GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
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GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
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GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
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GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
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GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
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GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
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GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
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GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
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GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
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GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
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GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
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GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
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GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
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GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
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GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
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GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
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GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
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GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
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GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
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GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
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GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
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GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
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GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
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GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
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GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
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GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
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GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
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GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
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GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
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GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
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GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
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GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
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GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
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GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
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GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
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GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
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GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
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GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
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GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
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EDIS;
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}
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//
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// End of File
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//
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