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465 lines
16 KiB
C
465 lines
16 KiB
C
//###########################################################################
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//
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// FILE: DSP2833x_ECan.c
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//
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// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions.
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//
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//###########################################################################
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// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
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// $Release Date: November 1, 2016 $
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// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
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// http://www.ti.com/ ALL RIGHTS RESERVED $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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//
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// InitECan - This function initializes the eCAN module to a known state.
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//
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void
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InitECan(void)
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{
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InitECana();
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#if DSP28_ECANB
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InitECanb();
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#endif // if DSP28_ECANB
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}
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//
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// InitECana - Initialize eCAN-A module
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//
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void
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InitECana(void)
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{
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//
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// Create a shadow register structure for the CAN control registers. This
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// is needed, since only 32-bit access is allowed to these registers.
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// 16-bit access to these registers could potentially corrupt the register
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// contents or return false data. This is especially true while writing
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// to/reading from a bit (or group of bits) among bits 16 - 31
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//
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struct ECAN_REGS ECanaShadow;
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EALLOW; // EALLOW enables access to protected bits
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//
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// Configure eCAN RX and TX pins for CAN operation using eCAN regs
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//
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ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
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ECanaShadow.CANTIOC.bit.TXFUNC = 1;
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ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
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ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
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ECanaShadow.CANRIOC.bit.RXFUNC = 1;
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ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
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//
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// Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
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// HECC mode also enables time-stamping feature
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//
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ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
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ECanaShadow.CANMC.bit.SCB = 1;
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ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
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//
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// Initialize all bits of 'Master Control Field' to zero
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// Some bits of MSGCTRL register come up in an unknown state. For proper
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// operation, all bits (including reserved bits) of MSGCTRL must be
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// initialized to zero
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//
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ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
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ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
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//
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// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
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// as a matter of precaution.
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//
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ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
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ECanaRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
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ECanaRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
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ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
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//
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// Configure bit timing parameters for eCANA
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//
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ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
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ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
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ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
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ECanaShadow.CANES.all = ECanaRegs.CANES.all;
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do
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{
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ECanaShadow.CANES.all = ECanaRegs.CANES.all;
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} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set
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ECanaShadow.CANBTC.all = 0;
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//
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// CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
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//
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#if (CPU_FRQ_150MHZ)
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//
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// The following block for all 150 MHz SYSCLKOUT
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// (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at End of File
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//
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ECanaShadow.CANBTC.bit.BRPREG = 4;
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ECanaShadow.CANBTC.bit.TSEG2REG = 2;
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ECanaShadow.CANBTC.bit.TSEG1REG = 10;
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#endif
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//
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// CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
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//
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#if (CPU_FRQ_100MHZ)
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//
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// The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock).
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// Bit rate = 1 Mbps See Note at End of File
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//
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ECanaShadow.CANBTC.bit.BRPREG = 4;
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ECanaShadow.CANBTC.bit.TSEG2REG = 1;
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ECanaShadow.CANBTC.bit.TSEG1REG = 6;
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#endif
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ECanaShadow.CANBTC.bit.SAM = 1;
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ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
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ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
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ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
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ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
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ECanaShadow.CANES.all = ECanaRegs.CANES.all;
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do
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{
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ECanaShadow.CANES.all = ECanaRegs.CANES.all;
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} while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared
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//
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// Disable all Mailboxes
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//
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ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
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EDIS;
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}
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#if (DSP28_ECANB)
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//
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// Initialize eCAN-B module
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//
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void
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InitECanb(void)
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{
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//
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// Create a shadow register structure for the CAN control registers. This
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// is needed, since only 32-bit access is allowed to these registers.
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// 16-bit access to these registers could potentially corrupt the register
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// contents or return false data. This is especially true while writing
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// to/reading from a bit (or group of bits) among bits 16 - 31
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//
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struct ECAN_REGS ECanbShadow;
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EALLOW; // EALLOW enables access to protected bits
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//
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// Configure eCAN RX and TX pins for CAN operation using eCAN regs
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//
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ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
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ECanbShadow.CANTIOC.bit.TXFUNC = 1;
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ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
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ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
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ECanbShadow.CANRIOC.bit.RXFUNC = 1;
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ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
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//
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// Configure eCAN for HECC mode - (read to access mailboxes 16 thru 31)
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//
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ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
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ECanbShadow.CANMC.bit.SCB = 1;
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ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
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//
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// Initialize all bits of 'Master Control Field' to zero
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// Some bits of MSGCTRL register come up in an unknown state. For proper
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// operation, all bits (including reserved bits) of MSGCTRL must be
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// initialized to zero
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//
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ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
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ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
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//
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// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
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// as a matter of precaution.
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//
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ECanbRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
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ECanbRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
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ECanbRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
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ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
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//
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// Configure bit timing parameters for eCANB
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//
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ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
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ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
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ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
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ECanbShadow.CANES.all = ECanbRegs.CANES.all;
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do
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{
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ECanbShadow.CANES.all = ECanbRegs.CANES.all;
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} while(ECanbShadow.CANES.bit.CCE != 1); // Wait for CCE bit to be cleared
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ECanbShadow.CANBTC.all = 0;
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//
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// CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
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//
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#if (CPU_FRQ_150MHZ)
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//
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// The following block for all 150 MHz SYSCLKOUT
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// (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at end of file
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//
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ECanbShadow.CANBTC.bit.BRPREG = 4;
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ECanbShadow.CANBTC.bit.TSEG2REG = 2;
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ECanbShadow.CANBTC.bit.TSEG1REG = 10;
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#endif
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//
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// CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
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//
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#if (CPU_FRQ_100MHZ)
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//
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// The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock).
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// Bit rate = 1 Mbps See Note at end of file
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//
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ECanbShadow.CANBTC.bit.BRPREG = 4;
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ECanbShadow.CANBTC.bit.TSEG2REG = 1;
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ECanbShadow.CANBTC.bit.TSEG1REG = 6;
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#endif
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ECanbShadow.CANBTC.bit.SAM = 1;
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ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
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ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
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ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
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ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
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ECanbShadow.CANES.all = ECanbRegs.CANES.all;
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do
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{
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ECanbShadow.CANES.all = ECanbRegs.CANES.all;
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} while(ECanbShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared
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//
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// Disable all Mailboxes
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//
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ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs
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EDIS;
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}
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#endif // if DSP28_ECANB
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//
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// InitECanGpio - This function initializes GPIO pins to function as eCAN pins
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//
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// Each GPIO pin can be configured as a GPIO pin or up to 3 different
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// peripheral functional pins. By default all pins come up as GPIO
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// inputs after reset.
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//
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// Caution:
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// Only one GPIO pin should be enabled for CANTXA/B operation.
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// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
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// Comment out other unwanted lines.
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//
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void
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InitECanGpio(void)
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{
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InitECanaGpio();
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#if (DSP28_ECANB)
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InitECanbGpio();
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#endif // if DSP28_ECANB
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}
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//
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// InitECanaGpio - This function initializes GPIO pins to function as eCAN- A
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//
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void
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InitECanaGpio(void)
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{
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EALLOW;
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//
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// Enable internal pull-up for the selected CAN pins
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// Pull-ups can be enabled or disabled by the user.
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// This will enable the pullups for the specified pins.
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// Comment out other unwanted lines.
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//
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// GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
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GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
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// GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; //Enable pull-up for GPIO31 (CANTXA)
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GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (CANTXA)
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//
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// Set qualification for selected CAN pins to asynch only
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// Inputs are synchronized to SYSCLKOUT by default.
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// This will select asynch (no qualification) for the selected pins.
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//
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// GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
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GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
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//
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// Configure eCAN-A pins using GPIO regs
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// This specifies which of the possible GPIO pins will be eCAN functional
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// pins.
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//
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// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA
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GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA
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// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA
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GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA
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EDIS;
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}
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#if (DSP28_ECANB)
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//
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// InitECanbGpio - This function initializes GPIO pins to function as eCAN-B
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//
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void
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InitECanbGpio(void)
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{
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EALLOW;
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//
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// Enable internal pull-up for the selected CAN pins
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// Pull-ups can be enabled or disabled by the user.
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// This will enable the pullups for the specified pins.
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// Comment out other unwanted lines.
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//
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// GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; //Enable pull-up for GPIO8 (CANTXB)
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//GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; //Enable pull-up for GPIO12(CANTXB)
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//GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up for GPIO16(CANTXB)
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GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; //Enable pull-up for GPIO20(CANTXB)
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// GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10(CANRXB)
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//GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13(CANRXB)
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//GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17(CANRXB)
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GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21(CANRXB)
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//
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// Set qualification for selected CAN pins to asynch only
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// Inputs are synchronized to SYSCLKOUT by default.
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// This will select asynch (no qualification) for the selected pins.
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// Comment out other unwanted lines.
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//
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// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
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//GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
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//GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
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GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
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//
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// Configure eCAN-B pins using GPIO regs
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// This specifies which of the possible GPIO pins will be eCAN functional
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// pins.
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//
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// GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB
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//GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB
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//GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB
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GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB
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|
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// GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB
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|
//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB
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//GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB
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GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB
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EDIS;
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}
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#endif // if DSP28_ECANB
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|
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//
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|
// Note: Bit timing parameters must be chosen based on the network parameters
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|
// such as the sampling point desired and the propagation delay of the network.
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|
// The propagation delay is a function of length of the cable, delay introduced
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|
// by the transceivers and opto/galvanic-isolators (if any).
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|
//
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|
// The parameters used in this file must be changed taking into account the
|
|
// above mentioned factors in order to arrive at the bit-timing parameters
|
|
// suitable for a network.
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//
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//
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// End of File
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//
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