/* * FRAMInterface.cpp * * Author: Aleksey Gerasimenko * gerasimenko.aleksey.n@gmail.com */ #include "PERIPHERY/FRAMInterface.h" namespace PERIPHERY { void write_fram(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) {} //CONSTRUCTOR FRAMInterface::FRAMInterface(): m_mode(PERIPHERY::FRAMInterface::WAIT), m_fifo_tx(), m_fifo_rx(), m_buffer_pointer(0), m_buffer_size(0), m_buffer_index(0), m_fram_start_addr(0), m_fram_addr(0), m_data_fram(0), m_data_buffer(0), m_data_variant(), m_verify_status(true), m_p_verify_status(0), m_destination(0), m_delay(0), _gpio_setup(SPIA_GPIO_SETUP_DEFAULT), _set_wp(SPIA_GPIO_WRITE_PROTECT_SET), _clear_wp(SPIA_GPIO_WRITE_PROTECT_CLEAR), _execute(&FRAMInterface::_execute_free) // {}//CONSTRUCTOR void FRAMInterface::setup() { SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Software Reset SPI SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Master SpiaRegs.SPICTL.bit.TALK = 1; // Talk // FRAM MODE 0 - CLKPOLARITY = 0, CLK_PHASE = 0 //SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase //SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // Shift Clock Polarity // FRAM MODE 3 - CLKPOLARITY = 1, CLK_PHASE = 0 SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase SpiaRegs.SPICCR.bit.CLKPOLARITY = 1; // Shift Clock Polarity SpiaRegs.SPICCR.bit.SPILBK = 0; // Loopback SpiaRegs.SPIBRR = 36; // Baud Rate = LSPCLK/(36+1) = 37.5MHz/(36+1) = 1MHz SpiaRegs.SPICCR.bit.SPICHAR = 7; // 8-bit word SpiaRegs.SPISTS.all = 0; // Clear OVERRUN_FLAG, INT_FLAG, BUFFULL_FLAG // FIFO SPI SpiaRegs.SPIFFTX.bit.SPIRST = 0; // Software reset FIFO SPI SpiaRegs.SPIFFTX.bit.SPIFFENA = 1; // Enable SPI FIFO SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // Release TX FIFO from Reset SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; // TXFIFO Interrupt Clear SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1; // Receive FIFO Overflow Clear SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1; // Receive FIFO Interrupt Clear //SpiaRegs.SPIFFTX.bit.TXFFIENA = 1; // TX FIFO Interrupt Enable //SpiaRegs.SPIFFRX.bit.RXFFIENA = 1; // RX FIFO Interrupt Enable SpiaRegs.SPIFFTX.bit.SPIRST = 1; // Release SPI FIFO SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; // Re-enable receive FIFO operation SpiaRegs.SPICCR.bit.SPISWRESET = 1; // Release SPI //SpiaRegs.SPICTL.bit.TALK = 1; // Talk (*_gpio_setup)(); (*_set_wp)(); SpiaRegs.SPITXBUF = FRAM_OPCODE_WREN; // m_delay = 8*150; // 8us * 150MHz = 1200 while(m_delay > 0){m_delay--;} while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // // SpiaRegs.SPITXBUF = FRAM_OPCODE_WRSR; SpiaRegs.SPITXBUF = 0; m_delay = 16*150; // 16us * 150MHz = 2400 while(m_delay > 0){m_delay--;} while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; _break_fram(); // }// // //#pragma CODE_SECTION("ramfuncs"); FRAMInterface::mode_t FRAMInterface::get_mode() { return m_mode; // }// // //#pragma CODE_SECTION("ramfuncs"); bool FRAMInterface::compare_mode(FRAMInterface::mode_t mode) { return mode == m_mode; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::break_fram() { _break_fram(); // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::write_buffer(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) { _prepare_execute(addr, buffer_pointer, buffer_size); // m_mode = FRAMInterface::WRITE; // _write_buffer(); // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::read_buffer(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) { _prepare_execute(addr, buffer_pointer, buffer_size); // m_mode = FRAMInterface::READ; // _execute = &FRAMInterface::_execute_read_buffer_get_data; _read_buffer_send_opcode(); // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::erase_buffer(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) { _prepare_execute(addr, buffer_pointer, buffer_size); // m_mode = FRAMInterface::ERASE; // _erase_buffer(); // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::verify_buffer(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size, bool *verify_status ) { _prepare_execute(addr, buffer_pointer, buffer_size); m_p_verify_status = verify_status; // m_mode = FRAMInterface::VERIFY; // _execute = &FRAMInterface::_execute_verify_buffer_data; //_execute = &FRAM::_execute_ready_verify_buffer; _verify_buffer_send_opcode(); // }// // void FRAMInterface::write_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) { m_mode = FRAMInterface::WRITE; _prepare_execute(addr, buffer_pointer, buffer_size); // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // clear receiver fifo registers while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; for(m_buffer_index = 0; m_buffer_index < m_buffer_size; m_buffer_index++) { _spi_opcode_wren(); m_delay = 8*150; // 8us * 150MHz = 1200 while(m_delay > 0){m_delay--;} // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // clear rx fifo buffer while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; m_data_buffer = *(m_buffer_pointer + m_buffer_index); m_data_variant.u16 = m_data_buffer; m_fram_addr = m_fram_start_addr + (m_buffer_index << 1); _spi_write_16(); // byte transmitted 8us // 5byte transmitted 5*8us // so pause 40us m_delay = 40*150; // 40us * 150MHz = 6000 while(m_delay > 0){m_delay--;} // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // clear rx fifo buffer while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; // }//for m_mode = FRAMInterface::WAIT; // }// void FRAMInterface::read_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) { m_mode = FRAMInterface::READ; _prepare_execute(addr, buffer_pointer, buffer_size); // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // clear receiver fifo registers while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; for(m_buffer_index = 0; m_buffer_index < m_buffer_size; m_buffer_index++) { m_fram_addr = m_fram_start_addr + (m_buffer_index << 1); _spi_read_16(); // byte transmitted 8us // 5byte transmitted 5*8us // so pause 40us m_delay = 40*150; // 40us * 150MHz = 6000 while(m_delay > 0){m_delay--;} // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} _spi_get_read_data_16(); m_data_fram = m_data_variant.u16; *(m_buffer_pointer + m_buffer_index) = m_data_fram; // }//for m_mode = FRAMInterface::WAIT; // }// void FRAMInterface::erase_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) { m_mode = FRAMInterface::WRITE; _prepare_execute(addr, buffer_pointer, buffer_size); // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // clear receiver fifo registers while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; for(m_buffer_index = 0; m_buffer_index < m_buffer_size; m_buffer_index++) { _spi_opcode_wren(); m_delay = 8*150; // 8us * 150MHz = 1200 while(m_delay > 0){m_delay--;} // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // clear rx fifo buffer while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; m_data_buffer = *(m_buffer_pointer + m_buffer_index); m_data_variant.u16 = m_data_buffer; m_fram_addr = m_fram_start_addr + (m_buffer_index << 1); _spi_erase_16(); // byte transmitted 8us // 5byte transmitted 5*8us // so pause 40us m_delay = 40*150; // 40us * 150MHz = 6000 while(m_delay > 0){m_delay--;} // waiting until all data will transmitted while(SpiaRegs.SPIFFTX.bit.TXFFST != 0){} // clear rx fifo buffer while(SpiaRegs.SPIFFRX.bit.RXFFST != 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; } // m_fifo_rx[0] = 0; // }//for m_mode = FRAMInterface::WAIT; // // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::write_int16 (uint16_t addr, int16_t data) { m_data_variant.i16 = data; m_fram_addr = addr; // _spi_write_16(); // m_mode = FRAMInterface::WRITE; // _execute = &FRAMInterface::_execute_write_register; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::write_uint16(uint16_t addr, uint16_t data) { m_data_variant.u16 = data; m_fram_addr = addr; // _spi_opcode_wren(); // m_mode = FRAMInterface::WRITE; // _execute = &FRAMInterface::_execute_ready_wren_write_uint16; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::write_int32 (uint16_t addr, int32_t data) { m_data_variant.i32 = data; m_fram_addr = addr; // _spi_write_32(); // m_mode = FRAMInterface::WRITE; // _execute = &FRAMInterface::_execute_write_register; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::write_uint32(uint16_t addr, uint32_t data) { m_data_variant.u32 = data; m_fram_addr = addr; // _spi_write_32(); // m_mode = FRAMInterface::WRITE; // _execute = &FRAMInterface::_execute_write_register; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::write_float (uint16_t addr, float data) { m_data_variant.f = data; m_fram_addr = addr; // _spi_write_32(); // m_mode = FRAMInterface::WRITE; // _execute = &FRAMInterface::_execute_write_register; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::write_bool (uint16_t addr, bool data) { m_data_variant.b = data; m_fram_addr = addr; // _spi_write_16(); // m_mode = FRAMInterface::WRITE; // _execute = &FRAMInterface::_execute_write_register; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::read_int16 (uint16_t addr, int16_t *destination) { m_data_variant.i16 = 0; m_fram_addr = addr; m_destination = destination; // _spi_read_16(); // m_mode = FRAMInterface::READ; // _execute = &FRAMInterface::_execute_ready_read_int16; // } // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::read_uint16(uint16_t addr, uint16_t *destination) { m_data_variant.u16 = 0; m_fram_addr = addr; m_destination = destination; // _spi_read_16(); // m_mode = FRAMInterface::READ; // _execute = &FRAMInterface::_execute_ready_read_uint16; // }// // void FRAMInterface::read_int32 (uint16_t addr, int32_t *destination) { m_data_variant.i32 = 0; m_fram_addr = addr; m_destination = destination; // _spi_read_32(); // m_mode = FRAMInterface::READ; // _execute = &FRAMInterface::_execute_ready_read_int32; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::read_uint32(uint16_t addr, uint32_t *destination) { m_data_variant.u32 = 0; m_fram_addr = addr; m_destination = destination; // _spi_read_32(); // m_mode = FRAMInterface::READ; // _execute = &FRAMInterface::_execute_ready_read_uint32; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::read_float (uint16_t addr, float *destination) { m_data_variant.f = 0; m_fram_addr = addr; m_destination = destination; // _spi_read_32(); // m_mode = FRAMInterface::READ; // _execute = &FRAMInterface::_execute_ready_read_float; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::read_bool (uint16_t addr, bool *destination) { m_data_variant.b = 0; m_fram_addr = addr; m_destination = destination; // _spi_read_32(); // m_mode = FRAMInterface::READ; // _execute = &FRAMInterface::_execute_ready_read_bool; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::set_wp() { (*_set_wp)(); // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::clear_wp() { (*_clear_wp)(); // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::execute() { (this->*_execute)(); // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_free() {}// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_write_buffer() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { // transmit FIFO is empty // if(m_buffer_index < m_buffer_size) { _spi_opcode_wren(); _execute = &FRAMInterface::_execute_ready_wren_write_buffer; // } else { _break_fram(); // }// if else // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_read_buffer_send_opcode() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { if(m_buffer_index < m_buffer_size) { m_fram_addr = m_fram_start_addr + (m_buffer_index << 1); _spi_read_16(); // } else { _break_fram(); // }// if else // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_read_buffer_get_data() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_16(); m_data_fram = m_data_variant.u16; *(m_buffer_pointer + m_buffer_index) = m_data_fram; m_buffer_index++; _read_buffer_send_opcode(); // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_read_status_register() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_status_register(); m_data_fram = m_data_variant.u16; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_erase_buffer() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { if(m_buffer_index < m_buffer_size) { _spi_opcode_wren(); _execute = &FRAMInterface::_execute_ready_wren_erase_buffer; // } else { _break_fram(); // }// if else // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_verify_buffer_send_opcode() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { if(m_buffer_index < m_buffer_size) { m_data_buffer = *(m_buffer_pointer + m_buffer_index); m_fram_addr = m_fram_start_addr + (m_buffer_index << 1); _spi_read_16(); // } else { *m_p_verify_status = m_verify_status; _break_fram(); // }// if else // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_verify_buffer_data() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_16(); m_data_fram = m_data_variant.u16; m_verify_status &= m_data_buffer == m_data_fram ? true : false; m_buffer_index++; _verify_buffer_send_opcode(); // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_break_fram() { m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_write_buffer() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_data_buffer = *(m_buffer_pointer + m_buffer_index); m_data_variant.u16 = m_data_buffer; m_fram_addr = m_fram_start_addr + (m_buffer_index << 1); m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_write_16(); m_buffer_index++; _execute = &FRAMInterface::_execute_ready_write_buffer; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_erase_buffer() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fram_addr = m_fram_start_addr + (m_buffer_index << 1); m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_erase_16(); m_buffer_index++; _execute = &FRAMInterface::_execute_ready_erase_buffer; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_write_buffer() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; _write_buffer(); // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_erase_buffer() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; _erase_buffer(); // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_write_int16() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_write_16(); _execute = &FRAMInterface::_execute_ready_write_int16; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_write_uint16() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_write_16(); _execute = &FRAMInterface::_execute_ready_write_uint16; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_write_int32() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_write_32(); _execute = &FRAMInterface::_execute_ready_write_int32; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_write_uint32() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_write_32(); _execute = &FRAMInterface::_execute_ready_write_uint32; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_write_float() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_write_32(); _execute = &FRAMInterface::_execute_ready_write_float; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_wren_write_bool() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; _spi_write_16(); _execute = &FRAMInterface::_execute_ready_write_bool; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_write_int16() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = 0; m_fifo_rx[6] = 0; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_write_uint16() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = 0; m_fifo_rx[6] = 0; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_write_int32() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = SpiaRegs.SPIRXBUF; m_fifo_rx[6] = SpiaRegs.SPIRXBUF; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_write_uint32() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = SpiaRegs.SPIRXBUF; m_fifo_rx[6] = SpiaRegs.SPIRXBUF; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_write_float() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = SpiaRegs.SPIRXBUF; m_fifo_rx[6] = SpiaRegs.SPIRXBUF; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_write_bool() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = 0; m_fifo_rx[6] = 0; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_read_int16() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_16(); *((int16_t*)m_destination) = m_data_variant.i16; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_read_uint16() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_16(); *((uint16_t*)m_destination) = m_data_variant.u16; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_read_int32() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_32(); *((int32_t*)m_destination) = m_data_variant.i32; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_read_uint32() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_32(); *((uint32_t*)m_destination) = m_data_variant.u32; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_read_float() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_32(); *((float*)m_destination) = m_data_variant.f; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_read_bool() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { _spi_get_read_data_16(); *((bool*)m_destination) = m_data_variant.b; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_write_register() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_write_16() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = 0; m_fifo_rx[6] = 0; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_opcode_wren() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { // m_fifo_rx[0] = SpiaRegs.SPIRXBUF; // m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_execute_ready_opcode_wrsr() { if(SpiaRegs.SPIFFTX.bit.TXFFST == 0) { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; // m_mode = FRAMInterface::WAIT; _execute = &FRAMInterface::_execute_free; // }//if // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_prepare_execute(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size) { m_fram_start_addr = addr; m_buffer_pointer = buffer_pointer; m_buffer_size = buffer_size; m_buffer_index = 0; m_fram_addr = 0; m_data_fram = 0; m_data_buffer = 0; m_verify_status = true; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_opcode_wren() { SpiaRegs.SPITXBUF = FRAM_OPCODE_WREN; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_opcode_wrsr() { SpiaRegs.SPITXBUF = FRAM_OPCODE_WRSR;; SpiaRegs.SPITXBUF = 0; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_write_16() { m_fifo_tx[0] = FRAM_OPCODE_WRITE; m_fifo_tx[1] = m_fram_addr & 0xff00; m_fifo_tx[2] = (m_fram_addr & 0x00ff) << 8; m_fifo_tx[3] = m_data_variant.u16 & 0xff00; m_fifo_tx[4] = (m_data_variant.u16 & 0x00ff) << 8; // SpiaRegs.SPITXBUF = m_fifo_tx[0]; SpiaRegs.SPITXBUF = m_fifo_tx[1]; SpiaRegs.SPITXBUF = m_fifo_tx[2]; SpiaRegs.SPITXBUF = m_fifo_tx[3]; SpiaRegs.SPITXBUF = m_fifo_tx[4]; // }// //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_erase_16() { m_fifo_tx[0] = FRAM_OPCODE_WRITE; m_fifo_tx[1] = m_fram_addr & 0xff00; m_fifo_tx[2] = (m_fram_addr & 0x00ff) << 8; m_fifo_tx[3] = FRAM_OPCODE_ERASE; m_fifo_tx[4] = FRAM_OPCODE_ERASE; // SpiaRegs.SPITXBUF = m_fifo_tx[0]; SpiaRegs.SPITXBUF = m_fifo_tx[1]; SpiaRegs.SPITXBUF = m_fifo_tx[2]; SpiaRegs.SPITXBUF = m_fifo_tx[3]; SpiaRegs.SPITXBUF = m_fifo_tx[4]; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_read_16() { m_fifo_tx[0] = FRAM_OPCODE_READ; m_fifo_tx[1] = (m_fram_addr & 0xff00); m_fifo_tx[2] = (m_fram_addr & 0x00ff) << 8; m_fifo_tx[3] = FRAM_OPCODE_DUMMY; m_fifo_tx[4] = FRAM_OPCODE_DUMMY; // SpiaRegs.SPITXBUF = m_fifo_tx[0]; SpiaRegs.SPITXBUF = m_fifo_tx[1]; SpiaRegs.SPITXBUF = m_fifo_tx[2]; SpiaRegs.SPITXBUF = m_fifo_tx[3]; SpiaRegs.SPITXBUF = m_fifo_tx[4]; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_get_read_data_16() { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; // m_data_variant.u16 = (uint16_t)(((m_fifo_rx[3] & 0x00ff) << 8) | (m_fifo_rx[4] & 0x00ff)); // }// // //#pragma CODE_SECTION("ramfuncs"); Uint16 FRAMInterface::_spi_get_fifo_tx_status() { return (Uint16)SpiaRegs.SPIFFTX.bit.TXFFST; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_write_32() { m_fifo_tx[0] = FRAM_OPCODE_WRITE; m_fifo_tx[1] = (m_fram_addr & 0xff00); m_fifo_tx[2] = (m_fram_addr & 0x00ff) << 8; m_fifo_tx[3] = m_data_variant.lw.wH.byte.high; m_fifo_tx[4] = m_data_variant.lw.wH.byte.low; m_fifo_tx[5] = m_data_variant.lw.wL.byte.high; m_fifo_tx[6] = m_data_variant.lw.wL.byte.low; // SpiaRegs.SPITXBUF = m_fifo_tx[0]; SpiaRegs.SPITXBUF = m_fifo_tx[1]; SpiaRegs.SPITXBUF = m_fifo_tx[2]; SpiaRegs.SPITXBUF = m_fifo_tx[3]; SpiaRegs.SPITXBUF = m_fifo_tx[4]; SpiaRegs.SPITXBUF = m_fifo_tx[5]; SpiaRegs.SPITXBUF = m_fifo_tx[6]; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_erase_32() { m_fifo_tx[0] = FRAM_OPCODE_WRITE; m_fifo_tx[1] = (m_fram_addr & 0xff00); m_fifo_tx[2] = (m_fram_addr & 0x00ff) << 8; m_fifo_tx[3] = FRAM_OPCODE_ERASE; m_fifo_tx[4] = FRAM_OPCODE_ERASE; m_fifo_tx[5] = FRAM_OPCODE_ERASE; m_fifo_tx[6] = FRAM_OPCODE_ERASE; // SpiaRegs.SPITXBUF = m_fifo_tx[0]; SpiaRegs.SPITXBUF = m_fifo_tx[1]; SpiaRegs.SPITXBUF = m_fifo_tx[2]; SpiaRegs.SPITXBUF = m_fifo_tx[3]; SpiaRegs.SPITXBUF = m_fifo_tx[4]; SpiaRegs.SPITXBUF = m_fifo_tx[5]; SpiaRegs.SPITXBUF = m_fifo_tx[6]; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_read_32() { m_fifo_tx[0] = FRAM_OPCODE_READ; m_fifo_tx[1] = (m_fram_addr & 0xff00); m_fifo_tx[2] = (m_fram_addr & 0x00ff) << 8; m_fifo_tx[3] = FRAM_OPCODE_DUMMY; m_fifo_tx[4] = FRAM_OPCODE_DUMMY; m_fifo_tx[5] = FRAM_OPCODE_DUMMY; m_fifo_tx[6] = FRAM_OPCODE_DUMMY; // SpiaRegs.SPITXBUF = m_fifo_tx[0]; SpiaRegs.SPITXBUF = m_fifo_tx[1]; SpiaRegs.SPITXBUF = m_fifo_tx[2]; SpiaRegs.SPITXBUF = m_fifo_tx[3]; SpiaRegs.SPITXBUF = m_fifo_tx[4]; SpiaRegs.SPITXBUF = m_fifo_tx[5]; SpiaRegs.SPITXBUF = m_fifo_tx[6]; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_get_read_data_32() { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = SpiaRegs.SPIRXBUF; m_fifo_rx[6] = SpiaRegs.SPIRXBUF; // m_data_variant.lw.wH.byte.high = m_fifo_rx[3]; m_data_variant.lw.wH.byte.low = m_fifo_rx[4]; m_data_variant.lw.wL.byte.high = m_fifo_rx[5]; m_data_variant.lw.wL.byte.low = m_fifo_rx[6]; // }// // //#pragma CODE_SECTION("ramfuncs"); void FRAMInterface::_spi_get_status_register() { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; // m_data_variant.lw.wL.byte.low = m_fifo_rx[1]; // }// // } /* namespace PERIPHERY */