/* * SPIA.cpp * * Author: Aleksey Gerasimenko * gerasimenko.aleksey.n@gmail.com */ #include "DSP28335/SPIA.h" namespace DSP28335 { //CONSTRUCTOR SPIA::SPIA(): SPIBase(), m_fifo_tx_status(0), m_data_tx_len(0), m_data_tx_counter(0), m_fifo_tx(), m_fifo_rx(), _gpio_setup(SPIA_GPIO_SETUP_DEFAULT) {}//CONSTRUCTOR void SPIA::setup() { SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Software Reset SPI SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Master // FRAM MODE 0 - CLKPOLARITY = 0, CLK_PHASE = 0 //SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase //SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // Shift Clock Polarity // FRAM MODE 3 - CLKPOLARITY = 1, CLK_PHASE = 0 SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase SpiaRegs.SPICCR.bit.CLKPOLARITY = 1; // Shift Clock Polarity SpiaRegs.SPICCR.bit.SPILBK = 0; // Loopback SpiaRegs.SPIBRR = 36; // Baud Rate = LSPCLK/(36+1) = 37.5MHz/(36+1) = 1MHz SpiaRegs.SPICCR.bit.SPICHAR = 7; // 8-bit word SpiaRegs.SPISTS.all = 0; // Clear OVERRUN_FLAG, INT_FLAG, BUFFULL_FLAG // FIFO SPI SpiaRegs.SPIFFTX.bit.SPIRST = 0; // Software reset FIFO SPI SpiaRegs.SPIFFTX.bit.SPIFFENA = 1; // Enable SPI FIFO SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // Release TX FIFO from Reset SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; // TXFIFO Interrupt Clear SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1; // Receive FIFO Overflow Clear SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1; // Receive FIFO Interrupt Clear SpiaRegs.SPIFFTX.bit.TXFFIENA = 1; // TX FIFO Interrupt Enable //SpiaRegs.SPIFFRX.bit.RXFFIENA = 1; // RX FIFO Interrupt Enable SpiaRegs.SPIFFTX.bit.SPIRST = 1; // Release SPI FIFO SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; // Re-enable receive FIFO operation SpiaRegs.SPICCR.bit.SPISWRESET = 1; // Release SPI (*_gpio_setup)(); // }// // void SPIA::setup(DSP28335::SPISetup& setup) { _gpio_setup = setup.gpio_setup; (*_gpio_setup)(); // }// // void SPIA::get_default_configuration(DSP28335::SPIConfiguration& config) { // }// // void SPIA::get_configuration(DSP28335::SPIConfiguration& config) { // }// // void SPIA::set_configuration(DSP28335::SPIConfiguration& config) { // }// // // #pragma CODE_SECTION("ramfuncs"); void SPIA::clear_tx_interrupt() { // Interrupt acknowledge SPITXINTA SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; // }// // // #pragma CODE_SECTION("ramfuncs"); void SPIA::write(Uint16 data, Uint16 addr) { m_fifo_tx[0] = FRAM_OPCODE_WREN; m_fifo_tx[1] = FRAM_OPCODE_WRITE; m_fifo_tx[2] = addr & 0xff00; m_fifo_tx[3] = (addr & 0x00ff) << 8; m_fifo_tx[4] = data & 0xff00; m_fifo_tx[5] = (data & 0x00ff) << 8; m_fifo_tx[6] = 0; m_fifo_tx[7] = 0; m_fifo_tx[8] = 0; m_fifo_tx[9] = 0; m_fifo_tx[10] = 0; m_fifo_tx[11] = 0; m_fifo_tx[12] = 0; m_fifo_tx[13] = 0; m_fifo_tx[14] = 0; m_fifo_tx[15] = 0; // m_data_tx_len = 6; SpiaRegs.SPIFFTX.bit.TXFIFO = 0; for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++) { SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter]; // }//for SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // }// // // #pragma CODE_SECTION("ramfuncs"); void SPIA::erase(Uint16 addr) { m_fifo_tx[0] = FRAM_OPCODE_WREN; m_fifo_tx[1] = FRAM_OPCODE_WRITE; m_fifo_tx[2] = addr & 0xff00; m_fifo_tx[3] = (addr & 0x00ff) << 8; m_fifo_tx[4] = FRAM_OPCODE_ERASE; m_fifo_tx[5] = FRAM_OPCODE_ERASE; m_fifo_tx[6] = 0; m_fifo_tx[7] = 0; m_fifo_tx[8] = 0; m_fifo_tx[9] = 0; m_fifo_tx[10] = 0; m_fifo_tx[11] = 0; m_fifo_tx[12] = 0; m_fifo_tx[13] = 0; m_fifo_tx[14] = 0; m_fifo_tx[15] = 0; // m_data_tx_len = 6; SpiaRegs.SPIFFTX.bit.TXFIFO = 0; for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++) { SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter]; // }//for SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // }// // // #pragma CODE_SECTION("ramfuncs"); void SPIA::read(Uint16 addr) { m_fifo_tx[0] = FRAM_OPCODE_READ; m_fifo_tx[1] = addr & 0xff00; m_fifo_tx[2] = (addr & 0x00ff) << 8; m_fifo_tx[3] = FRAM_OPCODE_DUMMY; m_fifo_tx[4] = FRAM_OPCODE_DUMMY; m_fifo_tx[5] = 0; m_fifo_tx[6] = 0; m_fifo_tx[7] = 0; m_fifo_tx[8] = 0; m_fifo_tx[9] = 0; m_fifo_tx[10] = 0; m_fifo_tx[11] = 0; m_fifo_tx[12] = 0; m_fifo_tx[13] = 0; m_fifo_tx[14] = 0; m_fifo_tx[15] = 0; m_data_tx_len = 5; SpiaRegs.SPIFFTX.bit.TXFIFO = 0; for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++) { SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter]; m_fifo_tx[m_data_tx_counter] = 0; // }//for SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // }// // // #pragma CODE_SECTION("ramfuncs"); Uint16 SPIA::get_read_data() { m_fifo_rx[0] = SpiaRegs.SPIRXBUF; m_fifo_rx[1] = SpiaRegs.SPIRXBUF; m_fifo_rx[2] = SpiaRegs.SPIRXBUF; m_fifo_rx[3] = SpiaRegs.SPIRXBUF; m_fifo_rx[4] = SpiaRegs.SPIRXBUF; m_fifo_rx[5] = 0; m_fifo_rx[6] = 0; m_fifo_rx[7] = 0; m_fifo_rx[8] = 0; m_fifo_rx[9] = 0; m_fifo_rx[10] = 0; m_fifo_rx[11] = 0; m_fifo_rx[12] = 0; m_fifo_rx[13] = 0; m_fifo_rx[14] = 0; m_fifo_rx[15] = 0; // return (Uint16)((m_fifo_rx[3] << 8) | (m_fifo_rx[4] & 0x00ff)); // }// // // #pragma CODE_SECTION("ramfuncs"); Uint16 SPIA::get_fifo_tx_status() { return m_fifo_tx_status = (Uint16)SpiaRegs.SPIFFTX.bit.TXFFST; // }// // void SPIA::_configure(DSP28335::SPIConfiguration& config) { // }// // } /* namespace DSP28335 */