/* * PWMInterface.h * * Author: Aleksey Gerasimenko * gerasimenko.aleksey.n@gmail.com */ #include #include #include "DSP28335/GPIO.h" #include "RUDRIVEFRAMEWORK/DataType.h" #include "RUDRIVEFRAMEWORK/SystemDefinitions.h" #include "PERIPHERY/PeripheryMap.h" #ifndef PERIPHERY_PWMINTERFACE_H_ #define PERIPHERY_PWMINTERFACE_H_ namespace PERIPHERY { struct PWMStructureSetup { pGPIO_FUNCTION p_gpio_hard_fault_setup; pGPIO_FUNCTION_UINT p_hard_fault_read; void set_default() { p_gpio_hard_fault_setup = &DSP28335::GPIO::gpio_hard_fault_setup; p_hard_fault_read = &DSP28335::GPIO::gpio_hard_fault_read; }; PWMStructureSetup(): p_gpio_hard_fault_setup(&DSP28335::GPIO::gpio_hard_fault_setup), p_hard_fault_read(&DSP28335::GPIO::gpio_hard_fault_read) {} };//PWMStructureSetup struct PWMBreakdownCellAddressFields { uint16_t cell: 3; uint16_t cascade: 5; uint16_t reserved: 8; };//PWMBreakdownCellAddressFields union PWMBreakdownCellAddressRegister { uint16_t all; PWMBreakdownCellAddressFields field; PWMBreakdownCellAddressRegister(): all(0) {} // };//PWMBreakdownCellAddressRegister struct PWMHardFaultBitField { uint16_t a: 1; uint16_t b: 1; uint16_t c: 1; // };//PWMHardFaultBitField union PWMHardFaultRegister { uint16_t all; PWMHardFaultBitField bit; PWMHardFaultRegister(): all(0) {} // };//PWMHardFaultRegister struct PWMBroadcastRegisters { uint16_t *p_order; uint16_t *p_cell_quantity_in_phase; uint16_t *p_freq; PWMBroadcastRegisters(): p_order(0), p_cell_quantity_in_phase(0), p_freq(0) {} };//PWMBroadCastRegisters struct PWMOffsetCells { uint16_t cell_offset[8]; PWMOffsetCells(): cell_offset() { cell_offset[0] = 0; cell_offset[1] = 1; cell_offset[2] = 2; cell_offset[3] = 3; cell_offset[4] = 4; cell_offset[5] = 5; cell_offset[6] = 6; cell_offset[7] = 7; } };//PWMOffsetCells struct PWMPhaseStructure { uint16_t *p_pwm_frequency; uint16_t *p_cell_quantity_in_phase; uint16_t *p_compare; uint16_t *p_order; uint16_t *p_pwm_state; uint16_t *p_pwm_version; uint16_t *a_cell_quantity_in_cascade[18]; uint16_t *a_cascade_pointers[18]; uint16_t *p_telemetry_box; uint16_t *p_breakdown_cell_state; uint16_t *p_breakdown_cell_address; PWMPhaseStructure(): p_pwm_frequency(), p_cell_quantity_in_phase(), p_compare(), p_order(), p_pwm_state(), p_pwm_version(), a_cell_quantity_in_cascade(), a_cascade_pointers(), p_telemetry_box(), p_breakdown_cell_state(), p_breakdown_cell_address() {} };//PWMPhaseStructure struct PWMPhaseValueStructure { uint16_t pwm_frequency; uint16_t cascade_quantity; uint16_t cell_quantity_in_phase; uint16_t cmp; uint16_t order; uint16_t pwm_state; uint16_t pwm_version; uint16_t cell_quantity_in_cascade[18]; uint16_t breakdown_cell_state; PWMBreakdownCellAddressRegister breakdown_cell_address; PWMPhaseValueStructure(): pwm_frequency(0), cascade_quantity(0), cell_quantity_in_phase(0), cmp(0), order(0), pwm_state(0), pwm_version(0), cell_quantity_in_cascade(), breakdown_cell_state(), breakdown_cell_address() {} };//PWMPhaseValueStructure struct PWMTelemetryFieldsOffset { uint16_t state; uint16_t saw_init_val; uint16_t version; uint16_t t_pcb; uint16_t ctrl_faults; uint16_t int_bd_l; uint16_t voltage; uint16_t freq_pwm; uint16_t time_cntr; uint16_t t_rad; uint16_t sync_faults; uint16_t int_bd_h; PWMTelemetryFieldsOffset( uint16_t state, uint16_t saw_init_val, uint16_t version, uint16_t t_pcb, uint16_t ctrl_faults, uint16_t int_bd_l, uint16_t voltage, uint16_t freq_pwm, uint16_t time_cntr, uint16_t t_rad, uint16_t sync_faults, uint16_t int_bd_h ): state(state), saw_init_val(saw_init_val), version(version), t_pcb(t_pcb), ctrl_faults(ctrl_faults), int_bd_l(int_bd_l), voltage(voltage), freq_pwm(freq_pwm), time_cntr(time_cntr), t_rad(t_rad), sync_faults(sync_faults), int_bd_h(int_bd_h) {} };//PWMTelemetryFieldsOffset struct PWMTelemetryCellFieldsValue { uint16_t state; uint16_t saw_init_val; uint16_t version; uint16_t t_pcb; uint16_t ctrl_faults; uint16_t int_bd_l; uint16_t voltage; uint16_t freq_pwm; uint16_t time_cntr; uint16_t t_rad; uint16_t sync_faults; uint16_t int_bd_h; PWMTelemetryCellFieldsValue(): state(0), saw_init_val(0), version(0), t_pcb(0), ctrl_faults(0), int_bd_l(0), voltage(0), freq_pwm(0), time_cntr(0), t_rad(0), sync_faults(0), int_bd_h(0) {} };//PWMTelemetryCellFieldsValue struct PWMCascadeTelemetryValue { PWMTelemetryCellFieldsValue cell[8]; PWMCascadeTelemetryValue(): cell() {} };//PWMCascadeTelemetryValue struct PWMPhaseTelemetryValue { PWMCascadeTelemetryValue cascade[18]; PWMPhaseTelemetryValue(): cascade() {} };//PWMPhaseTelemetryValue struct PWMStructureReference: public PWMPhaseValueStructure { uint16_t broadcast_order; uint16_t broadcast_cell_quantity; uint16_t broadcast_freq; PWMHardFaultRegister hard_fault; PWMStructureReference(): PWMPhaseValueStructure(), broadcast_order(0), broadcast_cell_quantity(0), broadcast_freq(0), hard_fault() {} };//PWMStructureReference struct PWMInterfaceConfiguration { float pwm_frequency; uint16_t adc_isr_quantity; float adc_isr_offset_relative; PWMInterfaceConfiguration(): pwm_frequency(500.0), adc_isr_quantity(1), adc_isr_offset_relative(FP_ZERO) {} // };//PWMInterfaceConfiguration struct PWMControlOrder { enum ORDER { START = 0x1111, // start the DVR, and cells start working and outputing STOP = 0x2222, // stop the DVR, and cells stop working and outputing RESET = 0x4444, // reset pwm fault and cells fault SELFCHECK = 0x8888 // make cells to check themselves };// }; class PWMInterface { protected: uint16_t m_counter_cascade; uint16_t m_counter_cells; uint16_t m_aux_offset; uint16_t m_aux_cell_quantity; uint16_t *m_aux_pointer; protected: uint16_t m_telemetry_function_counter; uint16_t m_telemetry_cascade_counter; uint16_t m_telemetry_cell_counter; uint16_t m_telemetry_function_quantity; uint16_t m_telemetry_cascade_quantity; uint16_t m_telemetry_cell_quantity; protected: PWMBroadcastRegisters m_broadcast; PWMTelemetryFieldsOffset m_telemetry_fields_offset; PWMOffsetCells m_offset_cells; PWMHardFaultRegister m_hard_fault; public: PWMInterface(); protected: void (*_gpio_hard_fault_setup)(); void (*_hard_fault_read)(uint16_t& data); }; } /* namespace PERIPHERY */ #endif /* PERIPHERY_PWMINTERFACE_H_ */