#pragma once #include namespace can_space { enum MBOX_NUMBERS { MODBUS_SETTINGS_MBOX = 0, COMM_VERSION_MBOX = 1, MODBUS_DATA_COMM_TO_CPU_RSV2_MBOX = 26, MODBUS_DATA_COMM_TO_CPU_RSV1_MBOX = 27, MODBUS_DATA_CPU_TO_COMM_MBOX = 28, MODBUS_DATA_COMM_TO_CPU_MBOX = 29, DIGITAL_INPUT_MBOX = 30, DIGITAL_OUTPUT_MBOX = 31 }; enum CAN_VARIANT{ CANA, CANB }; enum configFlags{ NONE = 0, MSB_ENABLE = 1u << 0, STM_ENABLE = 1u << 1 }; enum configSystemIsrFlags{ I0EN_ENABLE = 1ul, I1EN_ENABLE = 1ul << 1, GIL_ENABLE = 1ul << 2, WLIM_ENABLE = 1ul << 8, EPIM_ENABLE = 1ul << 9, BOIM_ENABLE = 1ul << 10, RMLIM_ENABLE = 1ul << 11, WUIM_ENABLE = 1ul << 12, WDIM_ENABLE = 1ul << 13, AAIM_ENABLE = 1ul << 14, TCOM_ENABLE = 1ul << 16, MTOM_ENABLE = 1ul << 17 }; // eCAN Message Control Register (MSGCTRL) bit definitions struct MsgCtrlBits { // bits description uint16_t DLC:4; // 0:3 uint16_t RTR:1; // 4 uint16_t OPC:1; // 1 uint16_t rsvd1:2; // 7:6 reserved uint16_t TPL:5; // 12:8 uint16_t rsvd2:3; // 15:13 reserved }; union MsgCtrlReg { uint16_t all; struct MsgCtrlBits bit; MsgCtrlReg(uint16_t configData = 0){ all = configData; } }; struct MsgID_Bits { // bits description uint16_t EXTMSGID_L:16; // 0:15 uint16_t EXTMSGID_H:2; // 16:17 uint16_t STDMSGID:11; // 18:28 uint16_t AAM:1; // 29 uint16_t AME:1; // 30 uint16_t IDE:1; // 31 }; // Allow access to the bit fields or entire register union MsgID { uint32_t all; struct MsgID_Bits bit; MsgID(uint32_t boxID = 0xAAA, bool isExtendedID = false, bool isAAM = false, bool isAME = false) { if(!isExtendedID){ bit.STDMSGID = boxID; bit.EXTMSGID_H = 0; bit.EXTMSGID_L = 0; } else{ all = boxID; } bit.IDE = isExtendedID; bit.AAM = isAAM; bit.AME = isAME; } MsgID(const MsgID& init) { all = init.all; } }; struct CANMessage { uint16_t dataLength; union CANMDL_REG mdl; union CANMDH_REG mdh; CANMessage(){ mdl.all = 0; mdh.all = 0; } }; }