/*
 * GPIO.cpp
 *
 *      Author: Aleksey Gerasimenko
 *      gerasimenko.aleksey.n@gmail.com
 */

#include "DSP28335/GPIO.h"

namespace DSP28335
{

//CONSTRUCTOR
GPIO::GPIO():
        DSP28335::CPUBase()
//
{}//end CONSTRUCTOR




//EPWM
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_epwm_setup()
{
    EALLOW;
    //
    // General Synchronization Signal GENSYNC - EPWM1A - GPIO0
    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;   // Configure GPIO0 as EPWM1A
    GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;    // Enable pull-up on GPIO0 (EPWM1A)
    GpioDataRegs.GPACLEAR.bit.GPIO0 = 1;  // Clear EPWM1A
    GpioCtrlRegs.GPADIR.bit.GPIO0 = 0;    // Output - EPWM1A
    //
    // Phase A (U) Synchronization Signal - EPWM5B - GPIO9
    GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;   // Configure GPIO9 as EPWM5B
    GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0;    // Disable pull-up on GPIO9 (EPWM5B)
    GpioDataRegs.GPACLEAR.bit.GPIO9 = 1;  // Clear EPWM5B
    GpioCtrlRegs.GPADIR.bit.GPIO9 = 0;    // Output - EPWM5B
    //
    // Phase B (V) Synchronization Signal - EPWM6A - GPIO10
    GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;   // Configure GPIO10 as EPWM6A
    GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;    // Disable pull-up on GPIO10 (EPWM6A)
    GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;  // Clear EPWM6A
    GpioCtrlRegs.GPADIR.bit.GPIO10 = 0;    // Output - EPWM6A
    //
    // Phase C (W) Synchronization Signal - EPWM6B - GPIO11
    GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;   // Configure GPIO9 as EPWM6B
    GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0;    // Disable pull-up on GPIO11 (EPWM6B)
    GpioDataRegs.GPACLEAR.bit.GPIO11 = 1;  // Clear EPWM6B
    GpioCtrlRegs.GPADIR.bit.GPIO11 = 0;    // Output - EPWM6B
    //
    EDIS;
    //
}//end
//

//CAN Inteface
void GPIO::gpio_cana_setup()
{
    EALLOW;
    //
    // Enable CANA on GPIO18, CPIO19
    // CANRXA - GPIO18
    // CANTXA - GPIO19
    //
    GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;   // Enable pullup on GPIO18
    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;  // GPIO18 = CANRXA
    GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input
    GpioCtrlRegs.GPADIR.bit.GPIO18 = 0;   // GPIO18 = 0/1 - input/output
    GpioDataRegs.GPASET.bit.GPIO18 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO18 = 0; // Clear output
    //
    GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;   // Enable pullup on GPIO19
    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;  // GPIO19 = CANTXA
    GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 0; // Asynch input
    GpioCtrlRegs.GPADIR.bit.GPIO19 = 0;   // GPIO19 = 0/1 - input/output
    GpioDataRegs.GPASET.bit.GPIO19 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO19 = 0; // Clear output
    //
    EDIS;
    //
}//end
//
void GPIO::gpio_canb_setup()
{
    EALLOW;
    //
    // Enable CANB on GPIO16, CPIO17
    // CANTXB - GPIO16
    // CANRXB - GPIO17
    //
    GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pullup on GPIO16
    GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2;  // GPIO16 = CANTXA
    GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 0; // Asynch input
    GpioCtrlRegs.GPADIR.bit.GPIO16 = 0;   // GPIO16 = 0/1 - input/output
    GpioDataRegs.GPASET.bit.GPIO16 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO16 = 0; // Clear output
    //
    GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pullup on GPIO17
    GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2;  // GPIO17 = CANRXA
    GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input
    GpioCtrlRegs.GPADIR.bit.GPIO17 = 0;   // GPIO17 = 0/1 - input/output
    GpioDataRegs.GPASET.bit.GPIO17 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO17 = 0; // Clear output
    //
    EDIS;
    //
}//end
//

//SCIA
void GPIO::gpio_scia_setup()
{}//

//
//RS485 - SCIB
void GPIO::gpio_scib_setup()
{
    EALLOW;
    //
    // Enable SCI-B on GPIO21, GPIO22, GPIO23 - RS485
    // SCIENBLB - GPIO21
    // SCITXDB - GPIO22
    // SCIRXDB - GPIO23
    //
    GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3;  // GPIO22 = SCITXDB
    GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0;   // Enable pullup on GPIO22
    GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Asynch input
    GpioCtrlRegs.GPADIR.bit.GPIO22 = 0;   // GPIO22 = 0/1 - input/output
    //
    GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3;  // GPIO23 = SCIRXDB
    GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0;   // Enable pullup on GPIO23
    GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input
    GpioCtrlRegs.GPADIR.bit.GPIO23 = 0;   // GPIO23 = 0/1 - input/output
    //
    EDIS;
    //
}//end
//
void GPIO::gpio_scib_re_de_setup()
{
    EALLOW;
    //
    // Enable SCI-B on GPIO21, GPIO22, GPIO23 - RS485
    // SCIENBLB - GPIO21
    // SCITXDB - GPIO22
    // SCIRXDB - GPIO23
    //
    GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0;  // GPIO21 = DE-RS485
    GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;   // Enable pullup on GPIO21
    GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;   // GPIO21 = 0/1 - input/output
    GpioDataRegs.GPASET.bit.GPIO21 = 0;     //
    GpioDataRegs.GPACLEAR.bit.GPIO21 = 0;   // Clear output
    //
    EDIS;
    //
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_scib_re_de_set()
{
    //set GPIO21
    GpioDataRegs.GPASET.bit.GPIO21 = 1;
    //
}//
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_scib_re_de_clear()
{
    //clear GPIO21
    GpioDataRegs.GPACLEAR.bit.GPIO21 = 1;
    //
}//
//
//RS485 - SCIC
void GPIO::gpio_scic_setup()
{
    EALLOW;
    //
    // Enable SCI-C on GPIO61, GPIO62, GPIO63 - RS485
    // SCIENBLC - GPIO61
    // SCIRXDC - GPIO62
    // SCITXDC - GPIO63
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0;  // GPIO61 = DE-RS485
    GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0;   // Enable pullup on GPIO61
    GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1;   // GPIO61 = 0/1 - input/output
    GpioDataRegs.GPBSET.bit.GPIO61 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO61 = 0; // Clear output
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1;  // GPIO62 = SCIRXDC
    GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0;   // Enable pullup on GPIO62
    GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input
    GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0;   // GPIO62 = 0/1 - input/output
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1;  // GPIO63 = SCITXDC
    GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0;   // Enable pullup on GPIO63
    GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Asynch input
    GpioCtrlRegs.GPBDIR.bit.GPIO63 = 0;   // GPIO63 = 0/1 - input/output
    //
    EDIS;
    //
}//end


//FRAM - SPIA
void GPIO::gpio_spia_setup()
{
    EALLOW;
    //
    //GPIO54 - SPISIMOA
    //GPIO55 - SPISOMIA
    //GPIO56 - SPICLKA
    //GPIO57 - SPISTEA
    //GPIO58 - SPISWP - Write Protect
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1;    // Configure GPIO54 as SPISIMOA
    GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0;     // Enable pull-up on GPIO54 (SPISIMOA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3;   // Asynch input GPIO54 (SPISIMOA)
    GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1;     // GPIO54 = 0/1 - input/output
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1;    // Configure GPIO55 as SPISOMIA
    GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0;     // Enable pull-up on GPIO55 (SPISOMIA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3;   // Asynch input GPIO55 (SPISOMIA)
    GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0;     // GPIO55 = 0/1 - input/output
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1;    // Configure GPIO56 as SPICLKA
    GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0;     // Enable pull-up on GPIO56 (SPICLKA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3;   // Asynch input GPIO56 (SPICLKA)
    GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1;     // GPIO56 = 0/1 - input/output
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1;    // Configure GPIO57 as SPISTEA
    GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0;     // Enable pull-up on GPIO57 (SPISTEA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3;   // Asynch input GPIO57 (SPISTEA)
    GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;     // GPIO57 = 0/1 - input/output
    //
    GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0;    // Configure GPIO58 as GPIO
    GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0;     // Enable pull-up on GPIO58
    GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;   // Asynch input GPIO58
    GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1;     // GPIO58 = 0/1 - input/output
    //
    EDIS;
    //
}//
//
void GPIO::gpio_spia_write_protect_set()
{
    GpioDataRegs.GPBSET.bit.GPIO58 = 1; // Set output
    //
}//
//
void GPIO::gpio_spia_write_protect_clear()
{
    GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1; // Set output
    //
}//
//



//
void GPIO::gpio_eqep_setup()
{
    EALLOW;
    //
    // Enable eQEP on GPIO50, CPIO51
    // EQEP1A - GPIO50
    // EQEP1B - GPIO51
    //
    GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0;   // Enable pullup on GPIO50
    GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1;  // GPIO50 = EQEP1A
    GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Asynch input
    GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0;   // GPIO50 = 0/1 - input/output
    GpioDataRegs.GPBSET.bit.GPIO50 = 1;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO50 = 0; // Clear output
    //
    GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0;   // Enable pullup on GPIO51
    GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1;  // GPIO51 = EQEP1B
    GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Asynch input
    GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0;   // GPIO51 = 0/1 - input/output
    GpioDataRegs.GPBSET.bit.GPIO51 = 1;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO51 = 0; // Clear output
    //
    EDIS;
    //
}//
//

void GPIO::gpio_xintf_16bit_setup()
{
    EALLOW;
    //
    // XINF - external interface
    //
    // GPIO34 - XREADY
    GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0;   // Enable pullup on GPIO34
    GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0;   // GPIO34 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3;  // GPIO34 = XREADY
    GpioDataRegs.GPBSET.bit.GPIO34 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO34 = 0; // Clear output
    //
    // GPIO35 - XR/nW
    GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0;   // Enable pullup on GPIO35
    GpioCtrlRegs.GPBDIR.bit.GPIO35 = 1;   // GPIO35 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3;  // GPIO35 = XR/nW
    GpioDataRegs.GPBSET.bit.GPIO35 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO35 = 0; // Clear output
    //
    // GPIO36 - nXZCS0
    GpioCtrlRegs.GPBPUD.bit.GPIO36 = 0;   // Enable pullup on GPIO36
    GpioCtrlRegs.GPBDIR.bit.GPIO36 = 1;   // GPIO36 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3;  // GPIO36 = nXZCS0
    GpioDataRegs.GPBSET.bit.GPIO36 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO36 = 0; // Clear output
    //
    // GPIO28 - nXZCS6
    GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;   // Enable pullup on GPIO28
    GpioCtrlRegs.GPADIR.bit.GPIO28 = 1;   // GPIO28 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Asynch input
    GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3;  // GPIO28 = nXZCS6
    GpioDataRegs.GPASET.bit.GPIO28 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO28 = 0; // Clear output
    //
    // GPIO37 - nXZCS7
    GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0;   // Enable pullup on GPIO37
    GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1;   // GPIO37 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;  // GPIO37 = nXZCS7
    GpioDataRegs.GPBSET.bit.GPIO37 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO37 = 0; // Clear output
    //
    // GPIO38 - nXWE0
    GpioCtrlRegs.GPBPUD.bit.GPIO38 = 0;   // Enable pullup on GPIO38
    GpioCtrlRegs.GPBDIR.bit.GPIO38 = 1;   // GPIO38 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO38 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3;  // GPIO38 = nXWE0
    GpioDataRegs.GPBSET.bit.GPIO38 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO38 = 0; // Clear output
    //
    // GPIO39 - XA16
    GpioCtrlRegs.GPBPUD.bit.GPIO39 = 0;   // Enable pullup on GPIO39
    GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0;   // GPIO39 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO39 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;  // GPIO39 = XA16
    GpioDataRegs.GPBSET.bit.GPIO39 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO39 = 0; // Clear output
    //
    // GPIO40 - XA0
    GpioCtrlRegs.GPBPUD.bit.GPIO40 = 0;   // Enable pullup on GPIO40
    GpioCtrlRegs.GPBDIR.bit.GPIO40 = 0;   // GPIO40 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO40 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3;  // GPIO40 = XA0
    GpioDataRegs.GPBSET.bit.GPIO40 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO40 = 0; // Clear output
    //
    // GPIO41 - XA1
    GpioCtrlRegs.GPBPUD.bit.GPIO41 = 0;   // Enable pullup on GPIO41
    GpioCtrlRegs.GPBDIR.bit.GPIO41 = 0;   // GPIO41 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO41 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3;  // GPIO41 = XA1
    GpioDataRegs.GPBSET.bit.GPIO41 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO41 = 0; // Clear output
    //
    // GPIO42 - XA2
    GpioCtrlRegs.GPBPUD.bit.GPIO42 = 0;   // Enable pullup on GPIO42
    GpioCtrlRegs.GPBDIR.bit.GPIO42 = 0;   // GPIO42 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO42 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3;  // GPIO42 = XA2
    GpioDataRegs.GPBSET.bit.GPIO42 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO42 = 0; // Clear output
    //
    // GPIO43 - XA3
    GpioCtrlRegs.GPBPUD.bit.GPIO43 = 0;   // Enable pullup on GPIO43
    GpioCtrlRegs.GPBDIR.bit.GPIO43 = 0;   // GPIO43 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO43 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3;  // GPIO43 = XA3
    GpioDataRegs.GPBSET.bit.GPIO43 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO43 = 0; // Clear output
    //
    // GPIO44 - XA4
    GpioCtrlRegs.GPBPUD.bit.GPIO44 = 0;   // Enable pullup on GPIO44
    GpioCtrlRegs.GPBDIR.bit.GPIO44 = 0;   // GPIO44 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO44 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3;  // GPIO44 = XA4
    GpioDataRegs.GPBSET.bit.GPIO44 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO44 = 0; // Clear output
    //
    // GPIO45 - XA5
    GpioCtrlRegs.GPBPUD.bit.GPIO45 = 0;   // Enable pullup on GPIO45
    GpioCtrlRegs.GPBDIR.bit.GPIO45 = 0;   // GPIO45 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO45 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3;  // GPIO45 = XA5
    GpioDataRegs.GPBSET.bit.GPIO45 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO45 = 0; // Clear output
    //
    // GPIO46 - XA6
    GpioCtrlRegs.GPBPUD.bit.GPIO46 = 0;   // Enable pullup on GPIO46
    GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0;   // GPIO46 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO46 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3;  // GPIO46 = XA6
    GpioDataRegs.GPBSET.bit.GPIO46 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO46 = 0; // Clear output
    //
    // GPIO47 - XA7
    GpioCtrlRegs.GPBPUD.bit.GPIO47 = 0;   // Enable pullup on GPIO47
    GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0;   // GPIO47 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO47 = 0; // Asynch input
    GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3;  // GPIO47 = XA7
    GpioDataRegs.GPBSET.bit.GPIO47 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO47 = 0; // Clear output
    //
    // GPIO80 - XA8
    GpioCtrlRegs.GPCPUD.bit.GPIO80 = 0;   // Enable pullup on GPIO80
    GpioCtrlRegs.GPCDIR.bit.GPIO80 = 0;   // GPIO80 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2;  // GPIO80 = XA8
    GpioDataRegs.GPCSET.bit.GPIO80 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO80 = 0; // Clear output
    //
    // GPIO81 - XA9
    GpioCtrlRegs.GPCPUD.bit.GPIO81 = 0;   // Enable pullup on GPIO81
    GpioCtrlRegs.GPCDIR.bit.GPIO81 = 0;   // GPIO81 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2;  // GPIO81 = XA9
    GpioDataRegs.GPCSET.bit.GPIO81 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO81 = 0; // Clear output
    //
    // GPIO82 - XA10
    GpioCtrlRegs.GPCPUD.bit.GPIO82 = 0;   // Enable pullup on GPIO82
    GpioCtrlRegs.GPCDIR.bit.GPIO82 = 0;   // GPIO82 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 2;  // GPIO82 = XA10
    GpioDataRegs.GPCSET.bit.GPIO82 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO82 = 0; // Clear output
    //
    // GPIO83 - XA11
    GpioCtrlRegs.GPCPUD.bit.GPIO83 = 0;   // Enable pullup on GPIO83
    GpioCtrlRegs.GPCDIR.bit.GPIO83 = 0;   // GPIO83 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 2;  // GPIO83 = XA11
    GpioDataRegs.GPCSET.bit.GPIO83 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO83 = 0; // Clear output
    //
    // GPIO84 - XA12
    GpioCtrlRegs.GPCPUD.bit.GPIO84 = 0;   // Enable pullup on GPIO84
    GpioCtrlRegs.GPCDIR.bit.GPIO84 = 0;   // GPIO84 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2;  // GPIO84 = XA12
    GpioDataRegs.GPCSET.bit.GPIO84 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO84 = 0; // Clear output
    //
    // GPIO85 - XA13
    GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0;   // Enable pullup on GPIO85
    GpioCtrlRegs.GPCDIR.bit.GPIO85 = 0;   // GPIO85 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2;  // GPIO85 = XA13
    GpioDataRegs.GPCSET.bit.GPIO85 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO85 = 0; // Clear output
    //
    // GPIO86 - XA14
    GpioCtrlRegs.GPCPUD.bit.GPIO86 = 0;   // Enable pullup on GPIO86
    GpioCtrlRegs.GPCDIR.bit.GPIO86 = 0;   // GPIO86 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2;  // GPIO86 = XA14
    GpioDataRegs.GPCSET.bit.GPIO86 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO86 = 0; // Clear output
    //
    // GPIO87 - XA15
    GpioCtrlRegs.GPCPUD.bit.GPIO87 = 0;   // Enable pullup on GPIO87
    GpioCtrlRegs.GPCDIR.bit.GPIO87 = 0;   // GPIO87 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2;  // GPIO87 = XA15
    GpioDataRegs.GPCSET.bit.GPIO87 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO87 = 0; // Clear output
    //
    // GPIO39 - XA16
    GpioCtrlRegs.GPBPUD.bit.GPIO39 = 0;   // Enable pullup on GPIO39
    GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0;   // GPIO39 = 0/1 - input/output
    GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;  // GPIO39 = XA16
    GpioDataRegs.GPBSET.bit.GPIO39 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO39 = 0; // Clear output
    //
    // GPIO31 - XA17
    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;   // Enable pullup on GPIO31
    GpioCtrlRegs.GPADIR.bit.GPIO31 = 0;   // GPIO31 = 0/1 - input/output
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3;  // GPIO31 = XA17
    GpioDataRegs.GPASET.bit.GPIO31 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO31 = 0; // Clear output
    //
    // GPIO30 - XA18
    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;   // Enable pullup on GPIO30
    GpioCtrlRegs.GPADIR.bit.GPIO30 = 0;   // GPIO30 = 0/1 - input/output
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3;  // GPIO30 = XA18
    GpioDataRegs.GPASET.bit.GPIO30 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO30 = 0; // Clear output

    // GPIO29 - XA19
    GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;   // Enable pullup on GPIO29
    GpioCtrlRegs.GPADIR.bit.GPIO29 = 0;   // GPIO29 = 0/1 - input/output
    GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3;  // GPIO29 = XA19
    GpioDataRegs.GPASET.bit.GPIO29 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO29 = 0; // Clear output
    //
    // GPIO64 - XD15
    GpioCtrlRegs.GPCPUD.bit.GPIO64 = 0;   // Enable pullup on GPIO64
    GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0;   // GPIO64 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 2;  // GPIO64 = XD
    GpioDataRegs.GPCSET.bit.GPIO64 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO64 = 0; // Clear output
    //
    // GPIO65 - XD14
    GpioCtrlRegs.GPCPUD.bit.GPIO65 = 0;   // Enable pullup on GPIO65
    GpioCtrlRegs.GPCDIR.bit.GPIO65 = 0;   // GPIO65 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 2;  // GPIO65 = XD14
    GpioDataRegs.GPCSET.bit.GPIO65 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO65 = 0; // Clear output
    //
    // GPIO66 - XD13
    GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0;   // Enable pullup on GPIO66
    GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0;   // GPIO66 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2;  // GPIO66 = XD13
    GpioDataRegs.GPCSET.bit.GPIO66 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO66 = 0; // Clear output
    //
    // GPIO67 - XD12
    GpioCtrlRegs.GPCPUD.bit.GPIO67 = 0;   // Enable pullup on GPIO67
    GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0;   // GPIO67 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 2;  // GPIO67 = XD12
    GpioDataRegs.GPCSET.bit.GPIO67 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO67 = 0; // Clear output
    //
    // GPIO68 - XD11
    GpioCtrlRegs.GPCPUD.bit.GPIO68 = 0;   // Enable pullup on GPIO68
    GpioCtrlRegs.GPCDIR.bit.GPIO68 = 0;   // GPIO68 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 2;  // GPIO68 = XD11
    GpioDataRegs.GPCSET.bit.GPIO68 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO68 = 0; // Clear output
    //
    // GPIO69 - XD10
    GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0;   // Enable pullup on GPIO69
    GpioCtrlRegs.GPCDIR.bit.GPIO69 = 0;   // GPIO69 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2;  // GPIO69 = XD10
    GpioDataRegs.GPCSET.bit.GPIO69 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO69 = 0; // Clear output
    //
    // GPIO70 - XD9
    GpioCtrlRegs.GPCPUD.bit.GPIO70 = 0;   // Enable pullup on GPIO70
    GpioCtrlRegs.GPCDIR.bit.GPIO70 = 0;   // GPIO70 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 2;  // GPIO70 = XD9
    GpioDataRegs.GPCSET.bit.GPIO70 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO70 = 0; // Clear output
    //
    // GPIO71 - XD8
    GpioCtrlRegs.GPCPUD.bit.GPIO71 = 0;   // Enable pullup on GPIO71
    GpioCtrlRegs.GPCDIR.bit.GPIO71 = 0;   // GPIO71 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 2;  // GPIO71 = XD8
    GpioDataRegs.GPCSET.bit.GPIO71 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO71 = 0; // Clear output
    //
    // GPIO72 - XD7
    GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0;   // Enable pullup on GPIO72
    GpioCtrlRegs.GPCDIR.bit.GPIO72 = 0;   // GPIO72 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 2;  // GPIO72 = XD7
    GpioDataRegs.GPCSET.bit.GPIO72 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO72 = 0; // Clear output
    //
    // GPIO73 - XD6
    GpioCtrlRegs.GPCPUD.bit.GPIO73 = 0;   // Enable pullup on GPIO73
    GpioCtrlRegs.GPCDIR.bit.GPIO73 = 0;   // GPIO73 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 2;  // GPIO73 = XD6
    GpioDataRegs.GPCSET.bit.GPIO73 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO73 = 0; // Clear output
    //
    // GPIO74 - XD5
    GpioCtrlRegs.GPCPUD.bit.GPIO74 = 0;   // Enable pullup on GPIO74
    GpioCtrlRegs.GPCDIR.bit.GPIO74 = 0;   // GPIO74 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 2;  // GPIO74 = XD5
    GpioDataRegs.GPCSET.bit.GPIO74 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO74 = 0; // Clear output
    //
    // GPIO75 - XD4
    GpioCtrlRegs.GPCPUD.bit.GPIO75 = 0;   // Enable pullup on GPIO75
    GpioCtrlRegs.GPCDIR.bit.GPIO75 = 0;   // GPIO75 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 2;  // GPIO75 = XD4
    GpioDataRegs.GPCSET.bit.GPIO75 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO75 = 0; // Clear output
    //
    // GPIO76 - XD3
    GpioCtrlRegs.GPCPUD.bit.GPIO76 = 0;   // Enable pullup on GPIO76
    GpioCtrlRegs.GPCDIR.bit.GPIO76 = 0;   // GPIO76 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 2;  // GPIO76 = XD3
    GpioDataRegs.GPCSET.bit.GPIO76 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO76 = 0; // Clear output
    //
    // GPIO77 - XD2
    GpioCtrlRegs.GPCPUD.bit.GPIO77 = 0;   // Enable pullup on GPIO77
    GpioCtrlRegs.GPCDIR.bit.GPIO77 = 0;   // GPIO77 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 2;  // GPIO77 = XD2
    GpioDataRegs.GPCSET.bit.GPIO77 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO77 = 0; // Clear output
    //
    // GPIO78 - XD1
    GpioCtrlRegs.GPCPUD.bit.GPIO78 = 0;   // Enable pullup on GPIO78
    GpioCtrlRegs.GPCDIR.bit.GPIO78 = 0;   // GPIO78 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2;  // GPIO78 = XD1
    GpioDataRegs.GPCSET.bit.GPIO78 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO78 = 0; // Clear output
    //
    // GPIO79 - XD0
    GpioCtrlRegs.GPCPUD.bit.GPIO79 = 0;   // Enable pullup on GPIO79
    GpioCtrlRegs.GPCDIR.bit.GPIO79 = 0;   // GPIO79 = 0/1 - input/output
    GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2;  // GPIO79 = XD0
    GpioDataRegs.GPCSET.bit.GPIO79 = 0;   //
    GpioDataRegs.GPCCLEAR.bit.GPIO79 = 0; // Clear output
    //
    EDIS;
    //
}//
//
void GPIO::gpio_xintf_32bit_setup()
{}//
//


void GPIO::gpio_dicrete_outputs_setup()
{
    EALLOW;
    //
    // GPIO1
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0;  // GPIO1
    GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1;   // Enable pullup on GPIO1
    GpioCtrlRegs.GPADIR.bit.GPIO1 = 1;   // GPIO1 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Asynch input
    GpioDataRegs.GPASET.bit.GPIO1 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO1 = 0; // Clear output
    //
    // GPIO2
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0;  // GPIO2
    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1;   // Enable pullup on GPIO2
    GpioCtrlRegs.GPADIR.bit.GPIO2 = 1;   // GPIO2 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0; // Asynch input
    GpioDataRegs.GPASET.bit.GPIO2 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO2 = 0; // Clear output
    //
    // GPIO3
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0;  // GPIO3
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1;   // Enable pullup on GPIO3
    GpioCtrlRegs.GPADIR.bit.GPIO3 = 1;   // GPIO3 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Asynch input
    GpioDataRegs.GPASET.bit.GPIO3 = 0;   //
    GpioDataRegs.GPACLEAR.bit.GPIO3 = 0; // Clear output
    //
    //
    // GPIO54
    GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 0;  // GPIO54
    GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0;   // Enable pullup on GPIO54
    GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1;   // GPIO54 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Asynch input
    GpioDataRegs.GPBSET.bit.GPIO54 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO54 = 0; // Clear output
    //
    // GPIO56
    GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0;  // GPIO56
    GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0;   // Enable pullup on GPIO56
    GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1;   // GPIO56 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Asynch input
    GpioDataRegs.GPBSET.bit.GPIO56 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO56 = 0; // Clear output
    //
    // GPIO57
    GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0;  // GPIO57
    GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0;   // Enable pullup on GPIO57
    GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;   // GPIO57 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Asynch input
    GpioDataRegs.GPBSET.bit.GPIO57 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO57 = 0; // Clear output
    //
    // GPIO58
    GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0;  // GPIO58
    GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0;   // Enable pullup on GPIO58
    GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1;   // GPIO58 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 0; // Asynch input
    GpioDataRegs.GPBSET.bit.GPIO58 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO58 = 0; // Clear output
    //
    // GPIO61
    GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0;  // GPIO61
    GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0;   // Enable pullup on GPIO61
    GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1;   // GPIO61 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 0; // Asynch input
    GpioDataRegs.GPBSET.bit.GPIO61 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO61 = 0; // Clear output
    //
    EDIS;
    //
}//
//

void GPIO::ext_adc_start_convertion_setup()
{
    EALLOW;
    // GPIO33
    GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0;  // GPIO33
    GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;   // Enable pullup on GPIO33
    GpioCtrlRegs.GPBDIR.bit.GPIO33 = 1;   // GPIO33 = 0/1 - input/output
    GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0; // Asynch input
    GpioDataRegs.GPBSET.bit.GPIO33 = 0;   //
    GpioDataRegs.GPBCLEAR.bit.GPIO33 = 0; // Clear output
    //
    EDIS;
    //
}//
//
void GPIO::set_ext_adc_start_convertion()
{
    //set GPIO33
    GpioDataRegs.GPBSET.bit.GPIO33 = 1;
    //
    //
}//
//
void GPIO::clear_ext_adc_start_convertion()
{
    //clear GPIO33
    GpioDataRegs.GPBCLEAR.bit.GPIO33 = 1;
    //
}//
//
void GPIO::gpio_hard_fault_setup()
{
    EALLOW;
    // GPIO4 - Fault A
    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0;  // GPIO4
    GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;   // Enable pullup on GPIO4
    GpioCtrlRegs.GPADIR.bit.GPIO4 = 0;   // GPIO4 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 0; // Asynch input
    //
    // GPIO6 - Fault B
    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0;  // GPIO6
    GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;   // Enable pullup on GPIO6
    GpioCtrlRegs.GPADIR.bit.GPIO6 = 0;   // GPIO6 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Asynch input
    //
    // GPIO8 - Fault C
    GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0;  // GPIO8
    GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0;   // Enable pullup on GPIO8
    GpioCtrlRegs.GPADIR.bit.GPIO8 = 0;   // GPIO8 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Asynch input
    //
    EDIS;
    //
}//
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_hard_fault_read(uint16_t& data)
{
    data = (uint16_t)((GpioDataRegs.GPADAT.bit.GPIO8 == 1 ? 0x4 : 0x0) |
            (GpioDataRegs.GPADAT.bit.GPIO6 == 1 ? 0x2 : 0x0) |
            (GpioDataRegs.GPADAT.bit.GPIO4 == 1 ? 0x1 : 0x0));
    //
}//
//

//
// Analog Alarm Current Sensors
void GPIO::gpio_analog_fault_setup()
{
    EALLOW;
    // GPIO12 - Analog Alarm 21
    GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;  // GPIO12
    GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;   // Enable pullup on GPIO12
    GpioCtrlRegs.GPADIR.bit.GPIO12 = 0;   // GPIO4 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Asynch input
    //
    // GPIO13 - Analog Alarm 22
    GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0;  // GPIO13
    GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;   // Enable pullup on GPIO13
    GpioCtrlRegs.GPADIR.bit.GPIO13 = 0;   // GPIO13 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Asynch input
    //
    // GPIO20 - Analog Alarm 20
    GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0;  // GPIO20
    GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;   // Enable pullup on GPIO20
    GpioCtrlRegs.GPADIR.bit.GPIO20 = 0;   // GPIO20 = 0/1 - input/output
    GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Asynch input
    //
    EDIS;
    //
    //
}//
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_analog_fault_read(uint16_t& data)
{
    data = (uint16_t)((GpioDataRegs.GPADAT.bit.GPIO12 == 1 ? 0x4 : 0x0) |
            (GpioDataRegs.GPADAT.bit.GPIO13 == 1 ? 0x2 : 0x0) |
            (GpioDataRegs.GPADAT.bit.GPIO20 == 1 ? 0x1 : 0x0));
    //
}//
//
} /* namespace DSP28335 */