diff --git a/28335_RAM_lnk.cmd b/28335_RAM_lnk.cmd new file mode 100644 index 0000000..0db663f --- /dev/null +++ b/28335_RAM_lnk.cmd @@ -0,0 +1,184 @@ +/* +// TI File $Revision: /main/11 $ +// Checkin $Date: April 15, 2009 09:57:28 $ +//########################################################################### +// +// FILE: 28335_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAML0, PAGE = 0 + #else + ramfuncs : > RAML0, PAGE = 0 + #endif +#endif + + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ \ No newline at end of file diff --git a/F28335/DSP2833x_ADC_cal.asm b/F28335/DSP2833x_ADC_cal.asm new file mode 100644 index 0000000..4866bb6 --- /dev/null +++ b/F28335/DSP2833x_ADC_cal.asm @@ -0,0 +1,45 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: July 30, 2007 10:29:23 $ +;;########################################################################### +;; +;; FILE: ADC_cal.asm +;; +;; TITLE: 2833x Boot Rom ADC Cal routine. +;; +;; Functions: +;; +;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and +;; ADCOFFTRIM registers +;; Notes: +;; +;;########################################################################### +;; $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +;; $Release Date: November 1, 2016 $ +;; $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +;; http://www.ti.com/ ALL RIGHTS RESERVED $ +;;########################################################################### + + .def _ADC_cal + .asg "0x711C", ADCREFSEL_LOC + +;----------------------------------------------- +; _ADC_cal +;----------------------------------------------- +;----------------------------------------------- +; This is the ADC cal routine.This routine is programmed into +; reserved memory by the factory. 0xAAAA and 0xBBBB are place- +; holders for calibration data. +;The actual values programmed by TI are device specific. +; +; This function assumes that the clocks have been +; enabled to the ADC module. +;----------------------------------------------- + + .sect ".adc_cal" + +_ADC_cal + MOVW DP, #ADCREFSEL_LOC >> 6 + MOV @28, #0xAAAA ; actual value may not be 0xAAAA + MOV @29, #0xBBBB ; actual value may not be 0xBBBB + LRETR +;eof ---------- diff --git a/F28335/DSP2833x_CodeStartBranch.asm b/F28335/DSP2833x_CodeStartBranch.asm new file mode 100644 index 0000000..8507428 --- /dev/null +++ b/F28335/DSP2833x_CodeStartBranch.asm @@ -0,0 +1,88 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: August 18, 2006 13:45:55 $ +;//########################################################################### +;// +;// FILE: DSP2833x_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example DSP2833x projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +;// $Release Date: November 1, 2016 $ +;// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +;// http://www.ti.com/ ALL RIGHTS RESERVED $ +;//########################################################################### + + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot.asm in RTS library + .endif + +;end codestart section + + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot.asm in RTS library + + .endif + +;end wd_disable + + + + .end + +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/F28335/DSP2833x_CpuTimers.c b/F28335/DSP2833x_CpuTimers.c new file mode 100644 index 0000000..fdce733 --- /dev/null +++ b/F28335/DSP2833x_CpuTimers.c @@ -0,0 +1,164 @@ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +// NOTES: CpuTimer2 is reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these this timer in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Defines +// +struct CPUTIMER_VARS CpuTimer0; + +// +// When using DSP BIOS & other RTOS, comment out CPU Timer 2 code. +// +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +// +// InitCpuTimers - This function initializes all three CPU timers to a known +// state. +// +void +InitCpuTimers(void) +{ + // + // CPU Timer 0 - Initialize address pointers to respective timer registers + // + CpuTimer0.RegsAddr = &CpuTimer0Regs; + + // + // Initialize timer period to maximum + // + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) + // + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + + // + // Make sure timer is stopped + // + CpuTimer0Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value + // + CpuTimer0Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters + // + CpuTimer0.InterruptCount = 0; + + // + // CpuTimer2 is reserved for DSP BIOS & other RTOS + // Do not use this timer if you ever plan on integrating + // DSP-BIOS or another realtime OS. + // + + // + // Initialize address pointers to respective timer registers + // + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + + // + // Initialize timer period to maximum + // + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + + // + // Make sure timers are stopped + // + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value + // + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters + // + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; +} + +// +// ConfigCpuTimer - This function initializes the selected timer to the period +// specified by the "Freq" and "Period" parameters. The "Freq" is entered as +// "MHz" and the period in "uSeconds". The timer is held in the stopped state +// after configuration. +// +void +ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // + // Initialize timer period + // + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + Timer->RegsAddr->PRD.all = temp; + + // + // Set pre-scale counter to divide by 1 (SYSCLKOUT) + // + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // + // Initialize timer control register + // + + // + // 1 = Stop timer, 0 = Start/Restart Timer + // + Timer->RegsAddr->TCR.bit.TSS = 1; + + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 1; + Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run + + // + // 0 = Disable/ 1 = Enable Timer Interrupt + // + Timer->RegsAddr->TCR.bit.TIE = 1; + + // + // Reset interrupt counter + // + Timer->InterruptCount = 0; +} + +// +// End of File +// + diff --git a/F28335/DSP2833x_DMA.c b/F28335/DSP2833x_DMA.c new file mode 100644 index 0000000..e35de45 --- /dev/null +++ b/F28335/DSP2833x_DMA.c @@ -0,0 +1,1287 @@ +//########################################################################### +// +// FILE: DSP2833x_DMA.c +// +// TITLE: DSP2833x Device DMA Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// DMAInitialize - This function initializes the DMA to a known state. +// +void +DMAInitialize(void) +{ + EALLOW; + + // + // Perform a hard reset on DMA + // + DmaRegs.DMACTRL.bit.HARDRESET = 1; + asm (" nop"); // one NOP required after HARDRESET + + // + // Allow DMA to run free on emulation suspend + // + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + +// +// DMACH1AddrConfig - +// +void +DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH1BurstConfig - +// +void +DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH1.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH1.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH1TransferConfig - +// +void +DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after + // completed transfer + // + DmaRegs.CH1.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH1WrapConfig - +// +void +DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 + deswstep) +{ + EALLOW; + + // + // Set up WRAP registers + // + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH1ModeConfig - +// +void +DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH1.MODE.bit.PERINTSEL = persel; + + DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16/32-bit data size transfers + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH1.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;// Clear any spurious interrupt flags + DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE + + EDIS; +} + +// +// StartDMACH1 - This function starts DMA Channel 1. +// +void +StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH2AddrConfig - +// +void +DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2BurstConfig - +// +void +DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH2.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH2.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH2TransferConfig - +// +void +DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur + // after completed transfer + // + DmaRegs.CH2.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH2WrapConfig - +// +void +DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + + // + // Wrap source address after N bursts + // + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; + + // + // Step for source wrap + // + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; + + // + // Wrap destination address after N bursts + // + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; + + // + // Step for destination wrap + // + DmaRegs.CH2.DST_WRAP_STEP = deswstep; + + EDIS; +} + +// +// DMACH2ModeConfig - +// +void +DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH2.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH2.MODE.bit.PERINTE = perinte; + + // + // Oneshot enable + // + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; + + // + // Continous enable + // + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; + + // + // Peripheral sync enable/disable + // + DmaRegs.CH2.MODE.bit.SYNCE = synce; + + // + // Sync effects source or destination + // + DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH2.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + + // + // Clear any spurious sync flags + // + DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; + + // + // Clear any spurious sync error flags + // + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt + // + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE + + EDIS; +} + +// +// StartDMACH2 - This function starts DMA Channel 2. +// +void +StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH3AddrConfig - +// +void +DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3BurstConfig - +// +void +DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH3.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH3.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH3TransferConfig - +// +void +DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after + // completed transfer + // + DmaRegs.CH3.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH3WrapConfig - +// +void +DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; + + // + // Step for destination wrap + // + DmaRegs.CH3.DST_WRAP_STEP = deswstep; + + EDIS; +} + +// +// DMACH3ModeConfig - +// +void +DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH3.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH3.MODE.bit.PERINTE = perinte; + + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH3.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE + + EDIS; +} + +// +// StartDMACH3 - This function starts DMA Channel 3. +// +void +StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH4AddrConfig - +// +void +DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4BurstConfig - +// +void +DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH4.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH4.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH4TransferConfig - +// +void +DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after completed + // transfer + // + DmaRegs.CH4.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH4WrapConfig - +// +void +DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep;// Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH4ModeConfig - +// +void +DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH4.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH4.MODE.bit.PERINTE = perinte; + + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH4.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE + + EDIS; +} + +// +// StartDMACH4 - This function starts DMA Channel 4. +// +void +StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH5AddrConfig - +// +void +DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5BurstConfig - +// +void +DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH5.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH5.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH5TransferConfig - +// +void +DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after completed + // transfer + // + DmaRegs.CH5.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH5WrapConfig - +// +void +DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep;// Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH5ModeConfig - +// +void +DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH5.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH5.MODE.bit.PERINTE = perinte; + + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH5.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE + + EDIS; +} + +// +// StartDMACH5 - This function starts DMA Channel 5. +// +void +StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH6AddrConfig - +// +void +DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + + // + // Point to beginning of source buffer + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; + + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + + // + // Point to beginning of destination buffer + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; + + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6BurstConfig - +// +void +DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + + // + // Number of words(X-1) x-ferred in a burst + // + DmaRegs.CH6.BURST_SIZE.all = bsize; + + // + // Increment source addr between each word x-ferred + // + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; + + // + // Increment dest addr between each word x-ferred + // + DmaRegs.CH6.DST_BURST_STEP = desbstep; + + EDIS; +} + +// +// DMACH6TransferConfig - +// +void +DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + + // + // Number of bursts per transfer, DMA interrupt will occur after completed + // transfer + // + DmaRegs.CH6.TRANSFER_SIZE = tsize; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; + + // + // TRANSFER_STEP is ignored when WRAP occurs + // + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; + + EDIS; +} + +// +// DMACH6WrapConfig - +// +void +DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize;// Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep;// Step for source wrap + + // + // Wrap destination address after N bursts + // + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; + + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH6ModeConfig - +// +void +DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, + Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // + + // + // Passed DMA channel as peripheral interrupt source + // + DmaRegs.CH6.MODE.bit.PERINTSEL = persel; + + // + // Peripheral interrupt enable + // + DmaRegs.CH6.MODE.bit.PERINTE = perinte; + + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable + DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable + + // + // Sync effects source or destination + // + DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; + + // + // Enable/disable the overflow interrupt + // + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; + + // + // 16-bit/32-bit data size transfers + // + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; + + // + // Generate interrupt to CPU at beginning/end of transfer + // + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; + + // + // Channel Interrupt to CPU enable + // + DmaRegs.CH6.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: + // + + // + // Clear any spurious interrupt flags + // + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; + + DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags + + // + // Clear any spurious sync error flags + // + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE + + EDIS; +} + +// +// StartDMACH6 - This function starts DMA Channel 6. +// +void +StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// End of File +// + diff --git a/F28335/DSP2833x_DefaultIsr.c b/F28335/DSP2833x_DefaultIsr.c new file mode 100644 index 0000000..0842ffc --- /dev/null +++ b/F28335/DSP2833x_DefaultIsr.c @@ -0,0 +1,1993 @@ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.c +// +// TITLE: DSP2833x Device Default Interrupt Service Routines. +// +// This file contains shell ISR routines for the 2833x PIE vector table. +// Typically these shell ISR routines can be used to populate the entire PIE +// vector table during device debug. In this manner if an interrupt is taken +// during firmware development, there will always be an ISR to catch it. +// +// As development progresses, these ISR routines can be eliminated and replaced +// with the user's own ISR routines for each interrupt. Since these shell ISRs +// include infinite loops they will typically not be included as-is in the final +// production firmware. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// INT13_ISR - Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +// +interrupt void +INT13_ISR(void) // INT13 or CPU-Timer1 +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT14_ISR - Note CPU-Timer2 is reserved for TI use. +// +interrupt void +INT14_ISR(void) // CPU-Timer2 +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DATALOG_ISR - Datalogging interrupt +// +interrupt void +DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOSINT_ISR - RTOS interrupt +// +interrupt void +RTOSINT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EMUINT_ISR - Emulation interrupt +// +interrupt void +EMUINT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// NMI_ISR - Non-maskable interrupt +// +interrupt void +NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ILLEGAL_ISR - Illegal operation TRAP +// +interrupt void +ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER1_ISR - User Defined trap 1 +// +interrupt void +USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER2_ISR - User Defined trap 2 +// +interrupt void +USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER3_ISR - User Defined trap 3 +// +interrupt void +USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER4_ISR - User Defined trap 4 +// +interrupt void +USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER5_ISR - User Defined trap 5 +// +interrupt void +USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER6_ISR - User Defined trap 6 +// +interrupt void +USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER7_ISR - User Defined trap 7 +// +interrupt void +USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER8_ISR - User Defined trap 8 +// +interrupt void +USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER9_ISR - User Defined trap 9 +// +interrupt void +USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER10_ISR - User Defined trap 10 +// +interrupt void +USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER11_ISR - User Defined trap 11 +// +interrupt void +USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER12_ISR - User Defined trap 12 +// +interrupt void +USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 1 - MUXed into CPU INT1 +// + +// +// SEQ1INT_ISR - INT1.1 +// +interrupt void +SEQ1INT_ISR(void) //SEQ1 ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SEQ2INT_ISR - INT1.2 +// +interrupt void +SEQ2INT_ISR(void) //SEQ2 ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + + asm(" ESTOP0"); + for(;;); +} + +// +// INT1.3 - Reserved +// + +// +// XINT1_ISR - INT1.4 +// +interrupt void +XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT2_ISR - INT1.5 +// +interrupt void +XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ADCINT_ISR - INT1.6 +// +interrupt void +ADCINT_ISR(void) // ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// TINT0_ISR - INT1.7 +// +interrupt void +TINT0_ISR(void) // CPU-Timer 0 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// WAKEINT_ISR - INT1.8 +// +interrupt void +WAKEINT_ISR(void) // WD, LOW Power +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 2 - MUXed into CPU INT2 +// + +// +// EPWM1_TZINT_ISR - INT2.1 +// +interrupt void +EPWM1_TZINT_ISR(void) // EPWM-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM2_TZINT_ISR - INT2.2 +// +interrupt void +EPWM2_TZINT_ISR(void) // EPWM-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM3_TZINT_ISR - INT2.3 +// +interrupt void +EPWM3_TZINT_ISR(void) // EPWM-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge + // this interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM4_TZINT_ISR - INT2.4 +// +interrupt void +EPWM4_TZINT_ISR(void) // EPWM-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM5_TZINT_ISR - INT2.5 +// +interrupt void +EPWM5_TZINT_ISR(void) // EPWM-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM6_TZINT_ISR - INT2.6 +// +interrupt void +EPWM6_TZINT_ISR(void) // EPWM-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT2.7 - Reserved +// + +// +// INT2.8 - Reserved +// + +// +// PIE Group 3 - MUXed into CPU INT3 +// + +// +// EPWM1_INT_ISR - INT 3.1 +// +interrupt void +EPWM1_INT_ISR(void) // EPWM-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM2_INT_ISR - INT3.2 +// +interrupt void +EPWM2_INT_ISR(void) // EPWM-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM3_INT_ISR - INT3.3 +// +interrupt void +EPWM3_INT_ISR(void) // EPWM-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM4_INT_ISR - INT3.4 +// +interrupt void +EPWM4_INT_ISR(void) // EPWM-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM5_INT_ISR - INT3.5 +// +interrupt void +EPWM5_INT_ISR(void) // EPWM-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM6_INT_ISR - INT3.6 +// +interrupt void +EPWM6_INT_ISR(void) // EPWM-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT3.7 - Reserved +// + +// +// INT3.8 - Reserved +// + +// +// PIE Group 4 - MUXed into CPU INT4 +// + +// +// ECAP1_INT_ISR - INT 4.1 +// +interrupt void +ECAP1_INT_ISR(void) // ECAP-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP2_INT_ISR - INT4.2 +// +interrupt void +ECAP2_INT_ISR(void) // ECAP-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP3_INT_ISR - INT4.3 +// +interrupt void +ECAP3_INT_ISR(void) // ECAP-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP4_INT_ISR - INT4.4 +// +interrupt void +ECAP4_INT_ISR(void) // ECAP-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP5_INT_ISR - INT4.5 +// +interrupt void +ECAP5_INT_ISR(void) // ECAP-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP6_INT_ISR - INT4.6 +// +interrupt void +ECAP6_INT_ISR(void) // ECAP-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT4.7 - Reserved +// + +// +// INT4.8 - Reserved +// + +// +// PIE Group 5 - MUXed into CPU INT5 +// + +// +// EQEP1_INT_ISR - INT 5.1 +// +interrupt void +EQEP1_INT_ISR(void) // EQEP-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EQEP2_INT_ISR - INT5.2 +// +interrupt void +EQEP2_INT_ISR(void) // EQEP-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT5.3 - Reserved +// + +// +// INT5.4 - Reserved +// + +// +// INT5.5 - Reserved +// + +// +// INT5.6 - Reserved +// + +// +// INT5.7 - Reserved +// + +// +// INT5.8 - Reserved +// + +// +// PIE Group 6 - MUXed into CPU INT6 +// + +// +// SPIRXINTA_ISR - INT6.1 +// +interrupt void +SPIRXINTA_ISR(void) // SPI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SPITXINTA_ISR - INT6.2 +// +interrupt void +SPITXINTA_ISR(void) // SPI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MRINTB_ISR - INT6.3 +// +interrupt void +MRINTB_ISR(void) // McBSP-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MXINTB_ISR - INT6.4 +// +interrupt void +MXINTB_ISR(void) // McBSP-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MRINTA_ISR - INT6.5 +// +interrupt void +MRINTA_ISR(void) // McBSP-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MXINTA_ISR - INT6.6 +// +interrupt void +MXINTA_ISR(void) // McBSP-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT6.7 - Reserved +// + +// +// INT6.8 - Reserved +// + +// +// PIE Group 7 - MUXed into CPU INT7 +// + +// +// DINTCH1_ISR - INT7.1 +// +interrupt void +DINTCH1_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH2_ISR - INT7.2 +// +interrupt void +DINTCH2_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH3_ISR - INT7.3 +// +interrupt void +DINTCH3_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH4_ISR - INT7.4 +// +interrupt void +DINTCH4_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH5_ISR - INT7.5 +// +interrupt void +DINTCH5_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH6_ISR - INT7.6 +// +interrupt void +DINTCH6_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT7.7 - Reserved +// + +// +// INT7.8 - Reserved +// + +// +// PIE Group 8 - MUXed into CPU INT8 +// + +// +// I2CINT1A_ISR - INT8.1 +// +interrupt void +I2CINT1A_ISR(void) // I2C-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// I2CINT2A_ISR - INT8.2 +// +interrupt void +I2CINT2A_ISR(void) // I2C-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT8.3 - Reserved +// + +// +// INT8.4 - Reserved +// + +// +// SCIRXINTC_ISR - INT8.5 +// +interrupt void +SCIRXINTC_ISR(void) // SCI-C +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTC_ISR - INT8.6 +// +interrupt void +SCITXINTC_ISR(void) // SCI-C +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT8.7 - Reserved +// + +// +// INT8.8 - Reserved +// + +// +// PIE Group 9 - MUXed into CPU INT9 +// + +// +// SCIRXINTA_ISR - INT9.1 +// +interrupt void +SCIRXINTA_ISR(void) // SCI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTA_ISR - INT9.2 +// +interrupt void +SCITXINTA_ISR(void) // SCI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCIRXINTB_ISR - INT9.3 +// +interrupt void +SCIRXINTB_ISR(void) // SCI-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTB_ISR - INT9.4 +// +interrupt void +SCITXINTB_ISR(void) // SCI-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN0INTA_ISR - INT9.5 +// +interrupt void +ECAN0INTA_ISR(void) // eCAN-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN1INTA_ISR - INT9.6 +// +interrupt void +ECAN1INTA_ISR(void) // eCAN-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN0INTB_ISR - INT9.7 +// +interrupt void +ECAN0INTB_ISR(void) // eCAN-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN1INTB_ISR - INT9.8 +// +interrupt void +ECAN1INTB_ISR(void) // eCAN-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 10 - MUXed into CPU INT10 +// + +// +// INT10.1 - Reserved +// + +// +// INT10.2 - Reserved +// + +// +// INT10.3 - Reserved +// + +// +// INT10.4 - Reserved +// + +// +// INT10.5 - Reserved +// + +// +// INT10.6 - Reserved +// + +// +// INT10.7 - Reserved +// + +// +// INT10.8 - Reserved +// + +// +// PIE Group 11 - MUXed into CPU INT11 +// + +// +// INT11.1 - Reserved +// + +// +// INT11.2 - Reserved +// + +// +// INT11.3 - Reserved +// + +// +// INT11.4 - Reserved +// + +// +// INT11.5 - Reserved +// + +// +// INT11.6 - Reserved +// + +// +// INT11.7 - Reserved +// + +// +// INT11.8 - Reserved +// + +// +// PIE Group 12 - MUXed into CPU INT12 +// + +// +// XINT3_ISR - INT12.1 +// +interrupt void +XINT3_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT4_ISR - INT12.2 +// +interrupt void +XINT4_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT5_ISR - INT12.3 +// +interrupt void +XINT5_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT6_ISR - INT12.4 +// +interrupt void +XINT6_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT7_ISR - INT12.5 +// +interrupt void +XINT7_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT12.6 - Reserved +// + +// +// LVF_ISR - INT12.7 +// +interrupt void +LVF_ISR(void) // Latched overflow +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// LUF_ISR - INT12.8 +// +interrupt void +LUF_ISR(void) // Latched underflow +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch All Default ISRs: +// + +// +// PIE_RESERVED - Reserved space. For test. +// +interrupt void +PIE_RESERVED(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// rsvd_ISR - For test +// +interrupt void +rsvd_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_ECan.c b/F28335/DSP2833x_ECan.c new file mode 100644 index 0000000..35971c4 --- /dev/null +++ b/F28335/DSP2833x_ECan.c @@ -0,0 +1,464 @@ +//########################################################################### +// +// FILE: DSP2833x_ECan.c +// +// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitECan - This function initializes the eCAN module to a known state. +// +void +InitECan(void) +{ + InitECana(); +#if DSP28_ECANB + InitECanb(); +#endif // if DSP28_ECANB +} + +// +// InitECana - Initialize eCAN-A module +// +void +InitECana(void) +{ + // + // Create a shadow register structure for the CAN control registers. This + // is needed, since only 32-bit access is allowed to these registers. + // 16-bit access to these registers could potentially corrupt the register + // contents or return false data. This is especially true while writing + // to/reading from a bit (or group of bits) among bits 16 - 31 + // + struct ECAN_REGS ECanaShadow; + + EALLOW; // EALLOW enables access to protected bits + + // + // Configure eCAN RX and TX pins for CAN operation using eCAN regs + // + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + // + // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) + // HECC mode also enables time-stamping feature + // + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // + // Initialize all bits of 'Master Control Field' to zero + // Some bits of MSGCTRL register come up in an unknown state. For proper + // operation, all bits (including reserved bits) of MSGCTRL must be + // initialized to zero + // + ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; + + // + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + // + ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits + + ECanaRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits + + ECanaRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits + ECanaRegs.CANGIF1.all = 0xFFFFFFFF; + + // + // Configure bit timing parameters for eCANA + // + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set + + ECanaShadow.CANBTC.all = 0; + + // + // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_150MHZ) + // + // The following block for all 150 MHz SYSCLKOUT + // (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at End of File + // + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 2; + ECanaShadow.CANBTC.bit.TSEG1REG = 10; + #endif + + // + // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_100MHZ) + // + // The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). + // Bit rate = 1 Mbps See Note at End of File + // + ECanaShadow.CANBTC.bit.BRPREG = 4; + ECanaShadow.CANBTC.bit.TSEG2REG = 1; + ECanaShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + ECanaShadow.CANBTC.bit.SAM = 1; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared + + // + // Disable all Mailboxes + // + ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} + +#if (DSP28_ECANB) +// +// Initialize eCAN-B module +// +void +InitECanb(void) +{ + // + // Create a shadow register structure for the CAN control registers. This + // is needed, since only 32-bit access is allowed to these registers. + // 16-bit access to these registers could potentially corrupt the register + // contents or return false data. This is especially true while writing + // to/reading from a bit (or group of bits) among bits 16 - 31 + // + struct ECAN_REGS ECanbShadow; + + EALLOW; // EALLOW enables access to protected bits + + // + // Configure eCAN RX and TX pins for CAN operation using eCAN regs + // + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + // + // Configure eCAN for HECC mode - (read to access mailboxes 16 thru 31) + // + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // + // Initialize all bits of 'Master Control Field' to zero + // Some bits of MSGCTRL register come up in an unknown state. For proper + // operation, all bits (including reserved bits) of MSGCTRL must be + // initialized to zero + // + ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000; + ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000; + + // + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + // + ECanbRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits + + ECanbRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits + + ECanbRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits + ECanbRegs.CANGIF1.all = 0xFFFFFFFF; + + // + // Configure bit timing parameters for eCANB + // + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1); // Wait for CCE bit to be cleared + + ECanbShadow.CANBTC.all = 0; + + // + // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_150MHZ) + // + // The following block for all 150 MHz SYSCLKOUT + // (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at end of file + // + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 2; + ECanbShadow.CANBTC.bit.TSEG1REG = 10; + #endif + + // + // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h + // + #if (CPU_FRQ_100MHZ) + // + // The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). + // Bit rate = 1 Mbps See Note at end of file + // + ECanbShadow.CANBTC.bit.BRPREG = 4; + ECanbShadow.CANBTC.bit.TSEG2REG = 1; + ECanbShadow.CANBTC.bit.TSEG1REG = 6; + #endif + + ECanbShadow.CANBTC.bit.SAM = 1; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared + + // + // Disable all Mailboxes + // + ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; +} +#endif // if DSP28_ECANB + +// +// InitECanGpio - This function initializes GPIO pins to function as eCAN pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for CANTXA/B operation. +// Only one GPIO pin shoudl be enabled for CANRXA/B operation. +// Comment out other unwanted lines. +// +void +InitECanGpio(void) +{ + InitECanaGpio(); +#if (DSP28_ECANB) + InitECanbGpio(); +#endif // if DSP28_ECANB +} + +// +// InitECanaGpio - This function initializes GPIO pins to function as eCAN- A +// +void +InitECanaGpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected CAN pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA) + //GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA) + + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; //Enable pull-up for GPIO31 (CANTXA) + //GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (CANTXA) + + // + // Set qualification for selected CAN pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA) + + // + // Configure eCAN-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAN functional + // pins. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA + //GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA + //GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA + + EDIS; +} + +#if (DSP28_ECANB) +// +// InitECanbGpio - This function initializes GPIO pins to function as eCAN-B +// +void +InitECanbGpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected CAN pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + // GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; //Enable pull-up for GPIO8 (CANTXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; //Enable pull-up for GPIO12(CANTXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up for GPIO16(CANTXB) + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; //Enable pull-up for GPIO20(CANTXB) + + // GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10(CANRXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13(CANRXB) + //GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17(CANRXB) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21(CANRXB) + + // + // Set qualification for selected CAN pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + // GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB) + + // + // Configure eCAN-B pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAN functional + // pins. + // + // GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB + //GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB + //GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB + + // GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB + //GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB + + EDIS; +} +#endif // if DSP28_ECANB + +// +// Note: Bit timing parameters must be chosen based on the network parameters +// such as the sampling point desired and the propagation delay of the network. +// The propagation delay is a function of length of the cable, delay introduced +// by the transceivers and opto/galvanic-isolators (if any). +// +// The parameters used in this file must be changed taking into account the +// above mentioned factors in order to arrive at the bit-timing parameters +// suitable for a network. +// + +// +// End of File +// + diff --git a/F28335/DSP2833x_ECap.c b/F28335/DSP2833x_ECap.c new file mode 100644 index 0000000..11ab3ff --- /dev/null +++ b/F28335/DSP2833x_ECap.c @@ -0,0 +1,273 @@ +//########################################################################### +// +// FILE: DSP2833x_ECap.c +// +// TITLE: DSP2833x eCAP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitECap - This function initializes the eCAP(s) to a known state. +// +void +InitECap(void) +{ + // + // Initialize eCAP1/2/3 + // +} + +// +// InitECapGpio - This function initializes GPIO pins to function as ECAP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eCAP peripheral +// Only one GPIO pin should be enabled for ECAP operation. +// Comment out other unwanted lines. +// +void +InitECapGpio() +{ + InitECap1Gpio(); +#if (DSP28_ECAP2) + InitECap2Gpio(); +#endif // endif DSP28_ECAP2 +#if (DSP28_ECAP3) + InitECap3Gpio(); +#endif // endif DSP28_ECAP3 +#if (DSP28_ECAP4) + InitECap4Gpio(); +#endif // endif DSP28_ECAP4 +#if (DSP28_ECAP5) + InitECap5Gpio(); +#endif // endif DSP28_ECAP5 +#if (DSP28_ECAP6) + InitECap6Gpio(); +#endif // endif DSP28_ECAP6 +} + +// +// InitECap1Gpio - +// +void +InitECap1Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1) + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1) + //GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; //Synch to SYSCLKOUT GPIO5 (CAP1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; //Synch to SYSCLKOUT GPIO24 (CAP1) + //GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; //Synch to SYSCLKOUT GPIO34 (CAP1) + + // + // Configure eCAP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAP1 functional pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1 + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1 + //GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1 + + EDIS; +} + +#if DSP28_ECAP2 +// +// InitECap2Gpio - +// +void +InitECap2Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2) + //GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2) + //GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; //Synch to SYSCLKOUT GPIO7 (CAP2) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; //Synch to SYSCLKOUT GPIO25 (CAP2) + //GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; //Synch to SYSCLKOUT GPIO37 (CAP2) + + // + // Configure eCAP-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eCAP2 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2 + //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2 + //GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2 + + EDIS; +} +#endif // endif DSP28_ECAP2 + +#if DSP28_ECAP3 +// +// InitECap3Gpio - +// +void +InitECap3Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3) +// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3) + +/* Configure eCAP-3 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP3 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3 +// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3 + + EDIS; +} +#endif // endif DSP28_ECAP3 + + +#if DSP28_ECAP4 +void InitECap4Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4) +// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4) +// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4) + +/* Configure eCAP-4 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP4 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4 +// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4 + + EDIS; +} +#endif // endif DSP28_ECAP4 + + +#if DSP28_ECAP5 +void InitECap5Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5) +// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP5 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5 +// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5 + + EDIS; +} +#endif // endif DSP28_ECAP5 + + +#if DSP28_ECAP6 +void InitECap6Gpio(void) +{ + EALLOW; + +/* Enable internal pull-up for the selected pins */ +// Pull-ups can be enabled or disabled by the user. +// This will enable the pullups for the specified pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6) +// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6) + +// Inputs are synchronized to SYSCLKOUT by default. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6) + +/* Configure eCAP-5 pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be eCAP6 functional pins. +// Comment out other unwanted lines. + + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6 +// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6 + + EDIS; +} +#endif // endif DSP28_ECAP6 + + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/F28335/DSP2833x_EPwm.c b/F28335/DSP2833x_EPwm.c new file mode 100644 index 0000000..4588a4b --- /dev/null +++ b/F28335/DSP2833x_EPwm.c @@ -0,0 +1,376 @@ +//########################################################################### +// +// FILE: DSP2833x_EPwm.c +// +// TITLE: DSP2833x ePWM Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitEPwm - This function initializes the ePWM(s) to a known state. +// +void +InitEPwm(void) +{ + // + // Initialize ePWM1/2/3/4/5/6 + // +} + +// +// InitEPwmGpio - This function initializes GPIO pins to function as ePWM pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +void +InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); +#if DSP28_EPWM4 + InitEPwm4Gpio(); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 + InitEPwm5Gpio(); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 + InitEPwm6Gpio(); +#endif // endif DSP28_EPWM6 +} + +// +// InitEPwm1Gpio - This function initializes GPIO pins to function as ePWM1 +// +void +InitEPwm1Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B) + + // + // Configure ePWM-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM1 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B + + EDIS; +} + +// +// InitEPwm2Gpio - This function initializes GPIO pins to function as ePWM2 +// +void +InitEPwm2Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B) + + // + // Configure ePWM-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM2 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B + + EDIS; +} + +// +// InitEPwm3Gpio - This function initializes GPIO pins to function as ePWM3 +// +void +InitEPwm3Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B) + + // + // Configure ePWM-3 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM3 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B + + EDIS; +} + +#if DSP28_EPWM4 +// +// InitEPwm4Gpio - This function initializes GPIO pins to function as ePWM4 +// +void +InitEPwm4Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B) + + // + // Configure ePWM-4 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM4 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B + + EDIS; +} +#endif // endif DSP28_EPWM4 + +#if DSP28_EPWM5 +// +// InitEPwm5Gpio - This function initializes GPIO pins to function as ePWM5 +// +void +InitEPwm5Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B) + + // + // Configure ePWM-5 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM5 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + + EDIS; +} +#endif // endif DSP28_EPWM5 + +#if DSP28_EPWM6 +// +// InitEPwm6Gpio - This function initializes GPIO pins to function as ePWM6 +// +void +InitEPwm6Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B) + + // + // Configure ePWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be ePWM6 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B + + EDIS; +} +#endif // endif DSP28_EPWM6 + +// +// InitEPwmSyncGpio - This function initializes GPIO pins to function as ePWM +// Synch pins +// +void +InitEPwmSyncGpio(void) +{ + EALLOW; + + // + // Configure EPWMSYNCI + // + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; //Enable pull-up on GPIO6 (EPWMSYNCI) + //GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;//Enable pull-up on GPIO32 (EPWMSYNCI) + + // + // Set qualification for selected pins to asynch only + // This will select synch to SYSCLKOUT for the selected pins. + // Comment out other unwanted lines. + // + + // + // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; + + // + //Synch to SYSCLKOUT GPIO32 (EPWMSYNCI) + // + //GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; + + // + // Configure EPwmSync pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPwmSync + // functional pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; //Enable pull-up on GPIO6(EPWMSYNCI) + //GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;//Enable pull-up on GPIO32(EPWMSYNCI) + + // + // Configure EPWMSYNC0 + // + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + + // + // Enable pull-up on GPIO6 (EPWMSYNC0) + // + //GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; + + // + // Enable pull-up on GPIO33 (EPWMSYNC0) + // + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; + + // + // Enable pull-up on GPIO6 (EPWMSYNC0) + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; + + // + // Enable pull-up on GPIO33 (EPWMSYNC0) + // + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; +} + +// +// InitTzGpio - This function initializes GPIO pins to function as Trip Zone +// (TZ) pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +void +InitTzGpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4) + + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5) + //GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5) + + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6) + //GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6) + + // + // Set qualification for selected pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1) + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2) + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3) + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6) + + // + // Configure TZ pins using GPIO regs + // This specifies which of the possible GPIO pins will be TZ functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4 + + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5 + //GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5 + + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6 + //GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6 + + EDIS; +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_EQep.c b/F28335/DSP2833x_EQep.c new file mode 100644 index 0000000..8adb9e5 --- /dev/null +++ b/F28335/DSP2833x_EQep.c @@ -0,0 +1,160 @@ +//########################################################################### +// +// FILE: DSP2833x_EQep.c +// +// TITLE: DSP2833x eQEP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitEQep - This function initializes the eQEP(s) to a known state. +// +void +InitEQep(void) +{ + // + // Initialize eQEP1/2 + // +} + +// +// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void +InitEQepGpio() +{ +#if DSP28_EQEP1 + InitEQep1Gpio(); +#endif // endif DSP28_EQEP1 +#if DSP28_EQEP2 + InitEQep2Gpio(); +#endif // endif DSP28_EQEP2 +} + +// +// InitEQep1Gpio - This function initializes GPIO pins to function as eQEP1 +// +#if DSP28_EQEP1 +void +InitEQep1Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I) + //GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A) + //GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B) + //GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S) + //GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I) + + //GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; //Sync to SYSCLKOUT GPIO50(EQEP1A) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; //Sync to SYSCLKOUT GPIO51(EQEP1B) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; //Sync to SYSCLKOUT GPIO52(EQEP1S) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; //Sync to SYSCLKOUT GPIO53(EQEP1I) + + // + // Configure eQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eQEP1 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I + + //GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A + //GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B + //GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S + //GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I + + EDIS; +} +#endif // if DSP28_EQEP1 + +// +// InitEQep2Gpio - This function initializes GPIO pins to function as eQEP2 +// +#if DSP28_EQEP2 +void +InitEQep2Gpio(void) +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S) + + // + // Inputs are synchronized to SYSCLKOUT by default. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S) + + // + // Configure eQEP-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be eQEP2 functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S + + EDIS; +} +#endif // endif DSP28_EQEP2 + +// +// End of file +// + diff --git a/F28335/DSP2833x_GlobalVariableDefs.c b/F28335/DSP2833x_GlobalVariableDefs.c new file mode 100644 index 0000000..8be4d20 --- /dev/null +++ b/F28335/DSP2833x_GlobalVariableDefs.c @@ -0,0 +1,376 @@ +//########################################################################### +// +// FILE: DSP2833x_GlobalVariableDefs.c +// +// TITLE: DSP2833x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +// +// Define Global Peripheral Variables +// +#ifdef __cplusplus +#pragma DATA_SECTION("AdcRegsFile") +#else +#pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); +#endif +volatile struct ADC_REGS AdcRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcMirrorFile") +#else +#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile"); +#endif +volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CsmPwlFile") +#else +#pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); +#endif +volatile struct CSM_PWL CsmPwl; + +#ifdef __cplusplus +#pragma DATA_SECTION("CsmRegsFile") +#else +#pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); +#endif +volatile struct CSM_REGS CsmRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("DevEmuRegsFile") +#else +#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); +#endif +volatile struct DEV_EMU_REGS DevEmuRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaRegsFile") +#else +#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); +#endif +volatile struct ECAN_REGS ECanaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMboxesFile") +#else +#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanaMboxes; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaLAMRegsFile") +#else +#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanaLAMRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanaMOTSRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTORegsFile") +#else +#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanaMOTORegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbRegsFile") +#else +#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile"); +#endif +volatile struct ECAN_REGS ECanbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMboxesFile") +#else +#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanbMboxes; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbLAMRegsFile") +#else +#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanbLAMRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTORegsFile") +#else +#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanbMOTORegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioIntRegsFile") +#else +#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile"); +#endif +volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct MCBSP_REGS McbspaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PartIdRegsFile") +#else +#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile"); +#endif +volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("SysCtrlRegsFile") +#else +#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); +#endif +volatile struct SYS_CTRL_REGS SysCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("FlashRegsFile") +#else +#pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); +#endif +volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("XIntruptRegsFile") +#else +#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); +#endif +volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("XintfRegsFile") +#else +#pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); +#endif +volatile struct XINTF_REGS XintfRegs; + +// +// End of file +// + diff --git a/F28335/DSP2833x_Gpio.c b/F28335/DSP2833x_Gpio.c new file mode 100644 index 0000000..7276375 --- /dev/null +++ b/F28335/DSP2833x_Gpio.c @@ -0,0 +1,77 @@ +//########################################################################### +// +// FILE: DSP2833x_Gpio.c +// +// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitGpio - This function initializes the Gpio to a known (default) state. +// +// For more details on configuring GPIO's as peripheral functions, +// refer to the individual peripheral examples and/or GPIO setup example. +// +void +InitGpio(void) +{ + EALLOW; + + // + // Each GPIO pin can be: + // a) a GPIO input/output + // b) peripheral function 1 + // c) peripheral function 2 + // d) peripheral function 3 + // By default, all are GPIO Inputs + // + GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 + GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 + GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39 + GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63 + GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 + GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 + + GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs + GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs + GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs + + // + // Each input can have different qualification + // a) input synchronized to SYSCLKOUT + // b) input qualified by a sampling window + // c) input sent asynchronously (valid for peripheral inputs only) + // + GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT + + // + // Pull-ups can be enabled or disabled + // + GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31 + GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63 + GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79 + //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31 + //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34 + //GpioCtrlRegs.GPCPUD.all = 0xFFFF; // Pullup's disabled GPIO64-GPIO79 + + EDIS; +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_I2C.c b/F28335/DSP2833x_I2C.c new file mode 100644 index 0000000..83bf050 --- /dev/null +++ b/F28335/DSP2833x_I2C.c @@ -0,0 +1,79 @@ +//########################################################################### +// +// FILE: DSP2833x_I2C.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitI2C - This function initializes the I2C to a known state. +// +void +InitI2C(void) +{ + // + // Initialize I2C-A + // +} + +// +// InitI2CGpio - This function initializes GPIO pins to function as I2C pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SDAA operation. +// Only one GPIO pin shoudl be enabled for SCLA operation. +// Comment out other unwanted lines. +// +void +InitI2CGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) + + // + // Set qualification for selected pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) + + // + // Configure SCI pins using GPIO regs + // This specifies which of the possible GPIO pins will be I2C functional + // pins. Comment out other unwanted lines. + // + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 to SDAA + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 to SCLA + + EDIS; +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_MemCopy.c b/F28335/DSP2833x_MemCopy.c new file mode 100644 index 0000000..6dbe540 --- /dev/null +++ b/F28335/DSP2833x_MemCopy.c @@ -0,0 +1,50 @@ +//########################################################################### +// +// FILE: DSP2833x_MemCopy.c +// +// TITLE: Memory Copy Utility +// +// ASSUMPTIONS: +// +// DESCRIPTION: +// +// This function will copy the specified memory contents from +// one location to another. +// +// Uint16 *SourceAddr Pointer to the first word to be moved +// SourceAddr < SourceEndAddr +// Uint16* SourceEndAddr Pointer to the last word to be moved +// Uint16* DestAddr Pointer to the first destination word +// +// No checks are made for invalid memory locations or that the +// end address is > then the first start address. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" + +// +// MemCopy - +// +void +MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) +{ + while(SourceAddr < SourceEndAddr) + { + *DestAddr++ = *SourceAddr++; + } + return; +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_PieCtrl.c b/F28335/DSP2833x_PieCtrl.c new file mode 100644 index 0000000..83fa8e6 --- /dev/null +++ b/F28335/DSP2833x_PieCtrl.c @@ -0,0 +1,95 @@ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.c +// +// TITLE: DSP2833x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a known +// state. +// +void +InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU interrupts +// +void +EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_PieVect.c b/F28335/DSP2833x_PieVect.c new file mode 100644 index 0000000..8ec72c0 --- /dev/null +++ b/F28335/DSP2833x_PieVect.c @@ -0,0 +1,231 @@ +//########################################################################### +// +// FILE: DSP2833x_PieVect.c +// +// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +const struct PIE_VECT_TABLE PieVectTableInit = +{ + PIE_RESERVED, // 0 Reserved space + PIE_RESERVED, // 1 Reserved space + PIE_RESERVED, // 2 Reserved space + PIE_RESERVED, // 3 Reserved space + PIE_RESERVED, // 4 Reserved space + PIE_RESERVED, // 5 Reserved space + PIE_RESERVED, // 6 Reserved space + PIE_RESERVED, // 7 Reserved space + PIE_RESERVED, // 8 Reserved space + PIE_RESERVED, // 9 Reserved space + PIE_RESERVED, // 10 Reserved space + PIE_RESERVED, // 11 Reserved space + PIE_RESERVED, // 12 Reserved space + + // + // Non-Peripheral Interrupts + // + INT13_ISR, // XINT13 or CPU-Timer 1 + INT14_ISR, // CPU-Timer2 + DATALOG_ISR, // Datalogging interrupt + RTOSINT_ISR, // RTOS interrupt + EMUINT_ISR, // Emulation interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + + // + // Group 1 PIE Vectors + // + SEQ1INT_ISR, // 1.1 ADC + SEQ2INT_ISR, // 1.2 ADC + rsvd_ISR, // 1.3 + XINT1_ISR, // 1.4 + XINT2_ISR, // 1.5 + ADCINT_ISR, // 1.6 ADC + TINT0_ISR, // 1.7 Timer 0 + WAKEINT_ISR, // 1.8 WD, Low Power + + // + // Group 2 PIE Vectors + // + EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone + EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone + EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone + EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone + EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone + EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone + rsvd_ISR, // 2.7 + rsvd_ISR, // 2.8 + + // + // Group 3 PIE Vectors + // + EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt + EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt + EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt + EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt + EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt + EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt + rsvd_ISR, // 3.7 + rsvd_ISR, // 3.8 + + // + // Group 4 PIE Vectors + // + ECAP1_INT_ISR, // 4.1 ECAP-1 + ECAP2_INT_ISR, // 4.2 ECAP-2 + ECAP3_INT_ISR, // 4.3 ECAP-3 + ECAP4_INT_ISR, // 4.4 ECAP-4 + ECAP5_INT_ISR, // 4.5 ECAP-5 + ECAP6_INT_ISR, // 4.6 ECAP-6 + rsvd_ISR, // 4.7 + rsvd_ISR, // 4.8 + + // + // Group 5 PIE Vectors + // + EQEP1_INT_ISR, // 5.1 EQEP-1 + EQEP2_INT_ISR, // 5.2 EQEP-2 + rsvd_ISR, // 5.3 + rsvd_ISR, // 5.4 + rsvd_ISR, // 5.5 + rsvd_ISR, // 5.6 + rsvd_ISR, // 5.7 + rsvd_ISR, // 5.8 + + // + // Group 6 PIE Vectors + // + SPIRXINTA_ISR, // 6.1 SPI-A + SPITXINTA_ISR, // 6.2 SPI-A + MRINTA_ISR, // 6.3 McBSP-A + MXINTA_ISR, // 6.4 McBSP-A + MRINTB_ISR, // 6.5 McBSP-B + MXINTB_ISR, // 6.6 McBSP-B + rsvd_ISR, // 6.7 + rsvd_ISR, // 6.8 + + // + // Group 7 PIE Vectors + // + DINTCH1_ISR, // 7.1 DMA channel 1 + DINTCH2_ISR, // 7.2 DMA channel 2 + DINTCH3_ISR, // 7.3 DMA channel 3 + DINTCH4_ISR, // 7.4 DMA channel 4 + DINTCH5_ISR, // 7.5 DMA channel 5 + DINTCH6_ISR, // 7.6 DMA channel 6 + rsvd_ISR, // 7.7 + rsvd_ISR, // 7.8 + + // + // Group 8 PIE Vectors + // + I2CINT1A_ISR, // 8.1 I2C + I2CINT2A_ISR, // 8.2 I2C + rsvd_ISR, // 8.3 + rsvd_ISR, // 8.4 + SCIRXINTC_ISR, // 8.5 SCI-C + SCITXINTC_ISR, // 8.6 SCI-C + rsvd_ISR, // 8.7 + rsvd_ISR, // 8.8 + + // + // Group 9 PIE Vectors + // + SCIRXINTA_ISR, // 9.1 SCI-A + SCITXINTA_ISR, // 9.2 SCI-A + SCIRXINTB_ISR, // 9.3 SCI-B + SCITXINTB_ISR, // 9.4 SCI-B + ECAN0INTA_ISR, // 9.5 eCAN-A + ECAN1INTA_ISR, // 9.6 eCAN-A + ECAN0INTB_ISR, // 9.7 eCAN-B + ECAN1INTB_ISR, // 9.8 eCAN-B + + // + // Group 10 PIE Vectors + // + rsvd_ISR, // 10.1 + rsvd_ISR, // 10.2 + rsvd_ISR, // 10.3 + rsvd_ISR, // 10.4 + rsvd_ISR, // 10.5 + rsvd_ISR, // 10.6 + rsvd_ISR, // 10.7 + rsvd_ISR, // 10.8 + + // + // Group 11 PIE Vectors + // + rsvd_ISR, // 11.1 + rsvd_ISR, // 11.2 + rsvd_ISR, // 11.3 + rsvd_ISR, // 11.4 + rsvd_ISR, // 11.5 + rsvd_ISR, // 11.6 + rsvd_ISR, // 11.7 + rsvd_ISR, // 11.8 + + // + // Group 12 PIE Vectors + // + XINT3_ISR, // 12.1 + XINT4_ISR, // 12.2 + XINT5_ISR, // 12.3 + XINT6_ISR, // 12.4 + XINT7_ISR, // 12.5 + rsvd_ISR, // 12.6 + LVF_ISR, // 12.7 + LUF_ISR, // 12.8 +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a known +// state. This function must be executed after boot time. +// +void +InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + volatile Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_Sci.c b/F28335/DSP2833x_Sci.c new file mode 100644 index 0000000..c9f4c00 --- /dev/null +++ b/F28335/DSP2833x_Sci.c @@ -0,0 +1,193 @@ +//########################################################################### +// +// FILE: DSP2833x_Sci.c +// +// TITLE: DSP2833x SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitSci - This function initializes the SCI(s) to a known state. +// +void +InitSci(void) +{ + // + // Initialize SCI-A + // + + // + // Initialize SCI-B + // + + // + // Initialize SCI-C + // +} + +// +// InitSciGpio - This function initializes GPIO to function as SCI-A, SCI-B, or +// SCI-C +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// Only one GPIO pin should be enabled for SCITXDA/B operation. +// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation. +// Comment out other unwanted lines. +// +void +InitSciGpio() +{ + InitSciaGpio(); +#if DSP28_SCIB + InitScibGpio(); +#endif // if DSP28_SCIB + +#if DSP28_SCIC + InitScicGpio(); +#endif // if DSP28_SCIC +} + +// +// InitSciaGpio - This function initializes GPIO pins to function as SCI-A pins +// +void +InitSciaGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) + + // + // Set qualification for selected pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) + + // + // Configure SCI-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be SCI functional + // pins. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 to SCIRXDA + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 to SCITXDA + + EDIS; +} + +#if DSP28_SCIB +// +// InitScibGpio - This function initializes GPIO pins to function as SCI-B pins +// +void +InitScibGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; //Enable pull-up for GPIO9 (SCITXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; //Enable pull-up for GPIO14 (SCITXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up for GPIO18 (SCITXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; //Enable pull-up for GPIO22 (SCITXDB) + + //GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; //Enable pull-up for GPIO11 (SCIRXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; //Enable pull-up for GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (SCIRXDB) + //GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; //Enable pull-up for GPIO23 (SCIRXDB) + + // + // Set qualification for selected pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB) + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB) + //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB) + + // + // Configure SCI-B pins using GPIO regs + // This specifies which of the possible GPIO pins will be SCI functional + // pins. + // Comment out other unwanted lines. + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; //Configure GPIO9 to SCITXDB + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; //Configure GPIO14 to SCITXDB + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; //Configure GPIO18 to SCITXDB + //GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; //Configure GPIO22 to SCITXDB + + //GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; //Configure GPIO11 for SCIRXDB + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; //Configure GPIO15 for SCIRXDB + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; //Configure GPIO19 for SCIRXDB + //GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; //Configure GPIO23 for SCIRXDB + + EDIS; +} +#endif // if DSP28_SCIB + +#if DSP28_SCIC +// +// InitScicGpio - This function initializes GPIO pins to function as SCI-C pins +// +void +InitScicGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled disabled by the user. + // This will enable the pullups for the specified pins. + // + GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC) + GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC) + + // + // Set qualification for selected pins to asynch only + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + // + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC) + + // + // Configure SCI-C pins using GPIO regs + // This specifies which of the possible GPIO pins will be SCI functional + // pins. + // + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 to SCIRXDC + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 to SCITXDC + + EDIS; +} +#endif // if DSP28_SCIC + +// +// End of file +// + diff --git a/F28335/DSP2833x_Spi.c b/F28335/DSP2833x_Spi.c new file mode 100644 index 0000000..353ea73 --- /dev/null +++ b/F28335/DSP2833x_Spi.c @@ -0,0 +1,113 @@ +//########################################################################### +// +// FILE: DSP2833x_Spi.c +// +// TITLE: DSP2833x SPI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitSPI - This function initializes the SPI(s) to a known state. +// +void +InitSpi(void) +{ + // + // Initialize SPI-A/B/C/D + // +} + +// +// InitSpiGpio - This function initializes GPIO pins to function as SPI pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// +// Caution: +// For each SPI peripheral +// Only one GPIO pin should be enabled for SPISOMO operation. +// Only one GPIO pin should be enabled for SPISOMI operation. +// Only one GPIO pin should be enabled for SPICLKA operation. +// Only one GPIO pin should be enabled for SPISTEA operation. +// Comment out other unwanted lines. +// +void +InitSpiGpio() +{ + InitSpiaGpio(); +} + +// +// InitSpiaGpio - This function initializes GPIO poins to function as SPI pins +// +void +InitSpiaGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up on GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; //Enable pull-up on GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up on GPIO19 (SPISTEA) + + //GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; //Enable pull-up on GPIO54 (SPISIMOA) + //GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; //Enable pull-up on GPIO55 (SPISOMIA) + //GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; //Enable pull-up on GPIO56 (SPICLKA) + //GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; //Enable pull-up on GPIO57 (SPISTEA) + + // + // Set qualification for selected pins to asynch only + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) + + //GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) + //GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) + + // + // Configure SPI-A pins using GPIO regs + // This specifies which of the possible GPIO pins will be SPI + // functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA + + //GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA + //GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA + //GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA + //GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA + + EDIS; +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_SysCtrl.c b/F28335/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..8bb7b0a --- /dev/null +++ b/F28335/DSP2833x_SysCtrl.c @@ -0,0 +1,422 @@ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: Example initialization of system resources. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. +// +#pragma CODE_SECTION(InitFlash, "ramfuncs"); + +// +// InitSysCtrl - This function initializes the System Control registers to a +// known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals +// +void +InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + + // + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + // + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // + // Initialize the peripheral clocks + // + InitPeripheralClocks(); +} + +// +// InitFlash - This function initializes the Flash Control registers +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +void +InitFlash(void) +{ + EALLOW; + + // + // Enable Flash Pipeline mode to improve performance + // of code executed from Flash. + // + FlashRegs.FOPT.bit.ENPIPE = 1; + + // + // CAUTION + // Minimum waitstates required for the flash operating + // at a given CPU rate must be characterized by TI. + // Refer to the datasheet for the latest information. + // +#if CPU_FRQ_150MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // + // CAUTION + // ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + // + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + // + // Force a pipeline flush to ensure that the write to + // the last register configured occurs before returning. + // + asm(" RPT #7 || NOP"); +} + +// +// ServiceDog - This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application +// +void +ServiceDog(void) +{ + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void +DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +// +// InitPll - This function initializes the PLLCR register. +// +void +InitPll(Uint16 val, Uint16 divsel) +{ + // + // Make sure the PLL is not running in limp mode + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + // + asm(" ESTOP0"); + } + + // + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + // + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // + // Change the PLLCR + // + if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + EALLOW; + + // + // Before setting PLLCR turn off missing clock detect logic + // + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = val; + EDIS; + + // + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + // + + // + // Wait for the PLL lock bit to be set. + // + + // + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + // + + // + // Uncomment to disable the watchdog + // + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // + // Uncomment to service the watchdog + // + //ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // + // If switching to 1/2 + // + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + // + // NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + // + if(divsel == 3) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } +} + +// +// InitPeripheralClocks - This function initializes the clocks to the +// peripheral modules. First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. To reduce power, leave +// clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral +// +void +InitPeripheralClocks(void) +{ + EALLOW; + + // + // HISPCP/LOSPCP prescale register settings, normally it will be set to + // default values + // + SysCtrlRegs.HISPCP.all = 0x0001; + SysCtrlRegs.LOSPCP.all = 0x0002; + + // + // XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + // + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + + // + // XCLKOUT = XTIMCLK/2 + // + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + // + // Enable XCLKOUT + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // Peripheral clock enables set for the selected peripherals. + // If you are not using a peripheral leave the clock off + // to save on power. + // + // Note: not all peripherals are available on all 2833x derivates. + // Refer to the datasheet for your particular device. + // + // This function is not written to be an example of efficient code. + // + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI + // reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + // + ADC_cal(); + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +Uint16 +CsmUnlock() +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // + // Perform a dummy read of the password locations if they match the key + // values, the CSM will unlock + // + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // + // If the CSM unlocked, return succes, otherwise return failure. + // + if (CsmRegs.CSMSCR.bit.SECURE == 0) + { + return STATUS_SUCCESS; + } + else + { + return STATUS_FAIL; + } +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_Xintf.c b/F28335/DSP2833x_Xintf.c new file mode 100644 index 0000000..ef81a42 --- /dev/null +++ b/F28335/DSP2833x_Xintf.c @@ -0,0 +1,303 @@ +//########################################################################### +// +// FILE: DSP2833x_Xintf.c +// +// TITLE: DSP2833x Device External Interface Init & Support Functions. +// +// DESCRIPTION: +// +// Example initialization function for the external interface (XINTF). +// This example configures the XINTF to its default state. For an +// example of how this function being used refer to the +// examples/run_from_xintf project. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitXINTF - This function initializes the External Interface the default +// reset state. +// +// Do not modify the timings of the XINTF while running from the XINTF. Doing +// so can yield unpredictable results +// +void +InitXintf(void) +{ + // + // This shows how to write to the XINTF registers. The + // values used here are the default state after reset. + // Different hardware will require a different configuration. + // + + // + // For an example of an XINTF configuration used with the + // F28335 eZdsp, refer to the examples/run_from_xintf project. + // + + // + // Any changes to XINTF timing should only be made by code + // running outside of the XINTF. + // + + // + // All Zones + // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT + // + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + + // + // No write buffering + // + XintfRegs.XINTCNF2.bit.WRBUFF = 0; + + // + // XCLKOUT is enabled + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // XCLKOUT = XTIMCLK/2 + // + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + // + // Zone 0 + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + // + XintfRegs.XTIMING0.bit.XWRLEAD = 3; + XintfRegs.XTIMING0.bit.XWRACTIVE = 7; + XintfRegs.XTIMING0.bit.XWRTRAIL = 3; + + // + // Zone read timing + // + XintfRegs.XTIMING0.bit.XRDLEAD = 3; + XintfRegs.XTIMING0.bit.XRDACTIVE = 7; + XintfRegs.XTIMING0.bit.XRDTRAIL = 3; + + // + // double all Zone read/write lead/active/trail timing + // + XintfRegs.XTIMING0.bit.X2TIMING = 1; + + // + // Zone will sample XREADY signal + // + XintfRegs.XTIMING0.bit.USEREADY = 1; + XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous + + // + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + // + XintfRegs.XTIMING0.bit.XSIZE = 3; + + // + // Zone 6 + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + // + XintfRegs.XTIMING6.bit.XWRLEAD = 3; + XintfRegs.XTIMING6.bit.XWRACTIVE = 7; + XintfRegs.XTIMING6.bit.XWRTRAIL = 3; + + // + // Zone read timing + // + XintfRegs.XTIMING6.bit.XRDLEAD = 3; + XintfRegs.XTIMING6.bit.XRDACTIVE = 7; + XintfRegs.XTIMING6.bit.XRDTRAIL = 3; + + // + // double all Zone read/write lead/active/trail timing + // + XintfRegs.XTIMING6.bit.X2TIMING = 1; + + // + // Zone will sample XREADY signal + // + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous + + // + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + // + XintfRegs.XTIMING6.bit.XSIZE = 3; + + // + // Zone 7 + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + // + XintfRegs.XTIMING7.bit.XWRLEAD = 3; + XintfRegs.XTIMING7.bit.XWRACTIVE = 7; + XintfRegs.XTIMING7.bit.XWRTRAIL = 3; + + // + // Zone read timing + // + XintfRegs.XTIMING7.bit.XRDLEAD = 3; + XintfRegs.XTIMING7.bit.XRDACTIVE = 7; + XintfRegs.XTIMING7.bit.XRDTRAIL = 3; + + // + // double all Zone read/write lead/active/trail timing + // + XintfRegs.XTIMING7.bit.X2TIMING = 1; + + // + // Zone will sample XREADY signal + // + XintfRegs.XTIMING7.bit.USEREADY = 1; + XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous + + // + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + // + XintfRegs.XTIMING7.bit.XSIZE = 3; + + // + // Bank switching + // Assume Zone 7 is slow, so add additional BCYC cycles + // when ever switching from Zone 7 to another Zone. + // This will help avoid bus contention. + // + XintfRegs.XBANK.bit.BANK = 7; + XintfRegs.XBANK.bit.BCYC = 7; + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + InitXintf16Gpio(); + //InitXintf32Gpio(); + + asm(" RPT #7 || NOP"); +} + +// +// InitXintf32Gpio - +// +void +InitXintf32Gpio() +{ + EALLOW; + GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31 + GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30 + GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29 + GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28 + GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27 + GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26 + GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25 + GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24 + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23 + GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22 + GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21 + GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20 + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19 + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18 + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17 + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16 + + GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input + + InitXintf16Gpio(); +} + +// +// InitXintf16Gpio - +// +void +InitXintf16Gpio() +{ + EALLOW; + GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 + GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 + GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 + GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n + GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 + GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 + GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 + GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 + GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 + GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 + GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 + + GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 + GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 + GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 + GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 + GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17 + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18 + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 + + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY + GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 + GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 + EDIS; +} + +// +// End of File +// + diff --git a/F28335/DSP2833x_usDelay.asm b/F28335/DSP2833x_usDelay.asm new file mode 100644 index 0000000..e0c8600 --- /dev/null +++ b/F28335/DSP2833x_usDelay.asm @@ -0,0 +1,78 @@ +;// TI File $Revision: /main/4 $ +;// Checkin $Date: July 30, 2007 10:28:57 $ +;//########################################################################### +;// +;// FILE: DSP2833x_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// +;// To use this function: +;// +;// 1 - update the CPU clock speed in the DSP2833x_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed +;// +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the DSP2833x_Examples.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// +;// extern void Delay(long LoopCount); +;// +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// +;// Or as follows (if count is less then 16-bits): +;// +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;// +;//########################################################################### +;// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +;// $Release Date: November 1, 2016 $ +;// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +;// http://www.ti.com/ ALL RIGHTS RESERVED $ +;//########################################################################### + + .def _DSP28x_usDelay + .sect "ramfuncs" + + .global __DSP28x_usDelay +_DSP28x_usDelay: + SUB ACC,#1 + BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/Protocol/CAN.cpp b/Protocol/CAN.cpp new file mode 100644 index 0000000..8e63be6 --- /dev/null +++ b/Protocol/CAN.cpp @@ -0,0 +1,188 @@ +#include "CAN.h" + +CAN::CAN(){ + +} + +void CAN::initGpio(CAN_VARIANT canVarinat){ + if(canVarinat == CAN_VARIAN::CANA) InitECanaGpio(); + else if (canVarinat == CAN_VARIAN::CANB) InitECanbGpio(); +} + +void CAN::config(CAN_VARIANT canVarinat, Uint16 baudrate){ + if (CAN == CANA){ + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1; + EDIS; + p_CanRegs_ = &ECanaRegs; + p_CanMBoxes_ = &ECanaMboxes; + } + else if (CAN == CANB){ + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1; + EDIS; + p_CanRegs_ = &ECanbRegs; + p_CanMBoxes_ = &ECanbMboxes; + } + else { return; } + + // + // Create a shadow register structure for the CAN control registers. This + // is needed, since only 32-bit access is allowed to these registers. + // 16-bit access to these registers could potentially corrupt the register + // contents or return false data. This is especially true while writing + // to/reading from a bit (or group of bits) among bits 16 - 31 + // + struct ECAN_REGS ECanShadow; + + EALLOW; // EALLOW enables access to protected bits + + // + // Configure eCAN RX and TX pins for CAN operation using eCAN regs + // + ECanShadow.CANTIOC.all = p_CanRegs_.CANTIOC.all; + ECanShadow.CANTIOC.bit.TXFUNC = 1; + p_CanRegs_.CANTIOC.all = ECanShadow.CANTIOC.all; + + ECanShadow.CANRIOC.all = p_CanRegs_.CANRIOC.all; + ECanShadow.CANRIOC.bit.RXFUNC = 1; + p_CanRegs_.CANRIOC.all = ECanShadow.CANRIOC.all; + + // + // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) + // HECC mode also enables time-stamping feature + // + ECanShadow.CANMC.all = p_CanRegs_.CANMC.all; + ECanShadow.CANMC.bit.SCB = 1; + p_CanRegs_.CANMC.all = ECanShadow.CANMC.all; + + // + // Initialize all bits of 'Master Control Field' to zero + // Some bits of MSGCTRL register come up in an unknown state. For proper + // operation, all bits (including reserved bits) of MSGCTRL must be + // initialized to zero + // + p_CanMBoxes_.MBOX0.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX1.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX2.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX3.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX4.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX5.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX6.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX7.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX8.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX9.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX10.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX11.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX12.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX13.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX14.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX15.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX16.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX17.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX18.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX19.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX20.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX21.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX22.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX23.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX24.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX25.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX26.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX27.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX28.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX29.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX30.MSGCTRL.all = 0x00000000; + p_CanMBoxes_.MBOX31.MSGCTRL.all = 0x00000000; + + // + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + // + p_CanRegs_.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits + + p_CanRegs_.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits + + p_CanRegs_.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits + p_CanRegs_.CANGIF1.all = 0xFFFFFFFF; + + // + // Configure bit timing parameters for eCANA + // + ECanShadow.CANMC.all = p_CanRegs_.CANMC.all; + ECanShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 + p_CanRegs_.CANMC.all = ECanShadow.CANMC.all; + + ECanShadow.CANES.all = p_CanRegs_.CANES.all; + + do + { + ECanShadow.CANES.all = p_CanRegs_.CANES.all; + } while(ECanShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set + + ECanShadow.CANBTC.all = 0; + + // The following block for all 150 MHz SYSCLKOUT + // (75 MHz CAN clock) - default. Bit rate = 1 Mbps + // + + switch (baudrate) { + case : 1000 + ECanShadow.CANBTC.bit.BRPREG = 4; + ECanShadow.CANBTC.bit.TSEG2REG = 3; + ECanShadow.CANBTC.bit.TSEG1REG = 9; + break; + + case : 500 + ECanShadow.CANBTC.bit.BRPREG = 9; + ECanShadow.CANBTC.bit.TSEG2REG = 3; + ECanShadow.CANBTC.bit.TSEG1REG = 9; + break; + + case : 250 + ECanShadow.CANBTC.bit.BRPREG = 19; + ECanShadow.CANBTC.bit.TSEG2REG = 3; + ECanShadow.CANBTC.bit.TSEG1REG = 9; + break; + + case : 100 + ECanShadow.CANBTC.bit.BRPREG = 49; + ECanShadow.CANBTC.bit.TSEG2REG = 3; + ECanShadow.CANBTC.bit.TSEG1REG = 9; + break; + + default: return; + } + + ECanShadow.CANBTC.bit.SAM = 1; + p_CanRegs_.CANBTC.all = ECanShadow.CANBTC.all; + + ECanShadow.CANMC.all = p_CanRegs_.CANMC.all; + ECanShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 + p_CanRegs_.CANMC.all = ECanShadow.CANMC.all; + + ECanShadow.CANES.all = p_CanRegs_.CANES.all; + + do + { + ECanShadow.CANES.all = p_CanRegs_.CANES.all; + } while(ECanShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared + + // + // Disable all Mailboxes + // + p_CanRegs_.CANME.all = 0; // Required before writing the MSGIDs + + EDIS; + + + +} + +void CAN::transmitMsg(){ + +} + +void CAN::receiveMsg(){ + +} diff --git a/Protocol/CAN.h b/Protocol/CAN.h new file mode 100644 index 0000000..c2e3a02 --- /dev/null +++ b/Protocol/CAN.h @@ -0,0 +1,25 @@ +#pragma once + +#include "DSP2833x_Device.h" +#include "DSP28x_Project.h" + +enum CAN_VARIANT{ + NONE = 0, + CANA, + CANB +}; + +class CAN{ +public: + CAN(); + + void initGpio(CAN_VARIANT canVarinat); + void config(CAN_VARIANT canVarinat, Uint16 baudrate); + + void transmitMsg(); + void receiveMsg(); + +private: + volatile struct ECAN_REGS* p_CanRegs_; + volatile struct ECAN_MBOXES* p_CanMBoxes_; +}; diff --git a/cmd/28335_RAM_lnk.cmd b/cmd/28335_RAM_lnk.cmd new file mode 100644 index 0000000..18d59bf --- /dev/null +++ b/cmd/28335_RAM_lnk.cmd @@ -0,0 +1,177 @@ +/* +//########################################################################### +// +// FILE: 28335_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + ramfuncs : > RAML0, PAGE = 0 + .text : > RAML1, PAGE = 0 + .InitBoot : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/cmd/DSP2833x_Headers_nonBIOS.cmd b/cmd/DSP2833x_Headers_nonBIOS.cmd new file mode 100644 index 0000000..9d3b6eb --- /dev/null +++ b/cmd/DSP2833x_Headers_nonBIOS.cmd @@ -0,0 +1,183 @@ +/* +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/cmd/F28335.cmd b/cmd/F28335.cmd new file mode 100644 index 0000000..fadb771 --- /dev/null +++ b/cmd/F28335.cmd @@ -0,0 +1,204 @@ +/* +//########################################################################### +// +// FILE: F28335.cmd +// +// TITLE: Linker Command File For F28335 Device +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ + RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ + RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ + RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ + RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ + RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > FLASHA PAGE = 0 + .pinit : > FLASHA, PAGE = 0 + .text : > FLASHA PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = FLASHD, + RUN = RAML0, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + LOAD_SIZE(_RamfuncsLoadSize), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAML7 PAGE = 1 // CHANGES RAMM1 was here. Also 0x400 was added in linker general options (in -heap) and 0x300 at stack was changed to 0x400 + .ebss : > RAML4 PAGE = 1 + .esysmem : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > FLASHA PAGE = 0 + .switch : > FLASHA PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/main.cpp b/main.cpp new file mode 100644 index 0000000..8c34739 --- /dev/null +++ b/main.cpp @@ -0,0 +1,111 @@ +// Some comments about author +#include +#include +#include +#include + + +#include "DSP28x_Project.h" // Device Headerfile and Examples Include File +#include "DSP2833x_Examples.h" +#include "SysConfig/f2833x_pinmux.h" +#include "Protocol/CAN.h" + + +//Functions declarations +void idle_loop(void); +interrupt void cpu_timer0_isr(void); +//interrupt void adc_isr(void); + + +void main() +{ + ServiceDog(); + DisableDog(); + + InitSysCtrl(); + + DINT; + + InitPieCtrl(); + + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + EALLOW; + PieVectTable.TINT0 = &cpu_timer0_isr; + EDIS; + +// memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize); + + // Call Flash Initialization to setup flash waitstates + // This function must reside in RAM +// InitFlash(); + + +// flash.setup(SECTORD, (Uint16*)0x320000, (Uint16*)0x327FFF); + +// configuration_parameters.setup(TIME_SAMPLE_CONTROL, TIME_SAMPLE_CONTROL_SLOW, TIME_SAMPLE_SERVICE, TPWM, FCPU, FPWM); +// configuration_parameters.load_flash(); + //configuration_parameters.extract_configuration(system_config); +// configuration_parameters.extract_configuration(test_config); + + InitCpuTimers(); + ConfigCpuTimer(&CpuTimer0, 150, 800); + + IER |= M_INT1; // Enable CPU Interrupt 1 + // Enable ADCINT in PIE +// PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + PieCtrlRegs.PIEIER1.bit.INTx7 = 1; + + + // + // Enable global Interrupts and higher priority real-time debug events: + // + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + + // + // Start CPU Timer + // +// core.cpu_timers.start(); + // + + InitECanGpio(); + InitECan(); + + CpuTimer0.RegsAddr->TCR.bit.TSS = 0; + + idle_loop(); + // +}//end main() +// +// + +void idle_loop() +{ + while (true) + { +/* + if (ECanaRegs.CANRMP.bit.RMP31) + { + GpioDataRegs.GPADAT.bit.GPIO14 = 1;} + else{ + GpioDataRegs.GPADAT.bit.GPIO14 = 0; + } +*/ + + + }//end while + // +}//end idle_loop() +// + +interrupt void cpu_timer0_isr(void) +{ + + // + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; +}//end diff --git a/targetConfigs/TMS320F28335.ccxml b/targetConfigs/TMS320F28335.ccxml new file mode 100644 index 0000000..e034bb0 --- /dev/null +++ b/targetConfigs/TMS320F28335.ccxml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targetConfigs/readme.txt b/targetConfigs/readme.txt new file mode 100644 index 0000000..d783fef --- /dev/null +++ b/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file