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233 lines
6.1 KiB
C++
233 lines
6.1 KiB
C++
4 weeks ago
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/*
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* XINTF.cpp
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*
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* Author: Aleksey Gerasimenko
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* gerasimenko.aleksey.n@gmail.com
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*/
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#include "DSP28335/XINTF.h"
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namespace DSP28335
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{
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//CONSTRUCTOR
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XINTF::XINTF():
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CPUBase(),
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_gpio_setup(&DSP28335::GPIO::gpio_xintf_16bit_setup)
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{}//CONSTRUCTOR
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void XINTF::setup(DSP28335::XINTFSetup& setup)
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{
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if(m_mode == DSP28335::XINTF::UNDEFINED)
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{
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//
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// This shows how to write to the XINTF registers. The
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// values used here are the default state after reset.
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// Different hardware will require a different configuration.
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//
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//
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// Any changes to XINTF timing should only be made by code
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// running outside of the XINTF.
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//
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//
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// All Zones
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// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
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//
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//struct XINTCNF2_BITS { // bits description
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// Uint16 WRBUFF:2; // 1:0 Write buffer depth
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// Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
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// Uint16 CLKOFF:1; // 3 Disable XCLKOUT
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// Uint16 rsvd1:2; // 5:4 reserved
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// Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
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// Uint16 rsvd2:1; // 8 reserved
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// Uint16 HOLD:1; // 9 Hold enable/disable
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// Uint16 HOLDS:1; // 10 Current state of HOLDn input
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// Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
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// Uint16 rsvd3:4; // 15:12 reserved
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// Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
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// Uint16 rsvd4:13; // 31:19 reserved
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//};
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EALLOW;
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XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
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//
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// No write buffering
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//
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XintfRegs.XINTCNF2.bit.WRBUFF = 0;
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//
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// XCLKOUT is enabled
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//
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XintfRegs.XINTCNF2.bit.CLKOFF = 0;
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//
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// XCLKOUT = XTIMCLK/2
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//
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XintfRegs.XINTCNF2.bit.CLKMODE = 1;
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//
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// WLEVEL
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//
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XintfRegs.XINTCNF2.bit.WLEVEL = 0;
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//
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// HOLD
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//
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XintfRegs.XINTCNF2.bit.HOLD = 0;
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//
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// HOLDS
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//
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XintfRegs.XINTCNF2.bit.HOLDS = 1;
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//
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// HOLDAS
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//
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XintfRegs.XINTCNF2.bit.HOLDAS = 1;
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//
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// Zone 0
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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//
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XintfRegs.XTIMING0.bit.XWRLEAD = 3;
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XintfRegs.XTIMING0.bit.XWRACTIVE = 5; // default 7;
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XintfRegs.XTIMING0.bit.XWRTRAIL = 1; // default 3;
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//
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// Zone read timing
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//
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XintfRegs.XTIMING0.bit.XRDLEAD = 3;
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XintfRegs.XTIMING0.bit.XRDACTIVE = 5; // default 7;
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XintfRegs.XTIMING0.bit.XRDTRAIL = 1; // default 3;
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//
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// double all Zone read/write lead/active/trail timing
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//
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XintfRegs.XTIMING0.bit.X2TIMING = 1;
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//
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// Zone will sample XREADY signal
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//
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XintfRegs.XTIMING0.bit.USEREADY = 1;
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XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
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//
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// Size must be either:
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// 0,1 = x32 or
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// 1,1 = x16 other values are reserved
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//
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XintfRegs.XTIMING0.bit.XSIZE = 3;
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//
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// Zone 6
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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//
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XintfRegs.XTIMING6.bit.XWRLEAD = 3;
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XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
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XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
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//
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// Zone read timing
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//
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XintfRegs.XTIMING6.bit.XRDLEAD = 3;
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XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
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XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
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//
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// double all Zone read/write lead/active/trail timing
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//
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XintfRegs.XTIMING6.bit.X2TIMING = 1;
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//
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// Zone will sample XREADY signal
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//
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XintfRegs.XTIMING6.bit.USEREADY = 1;
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XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
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//
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// Size must be either:
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// 0,1 = x32 or
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// 1,1 = x16 other values are reserved
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//
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XintfRegs.XTIMING6.bit.XSIZE = 3;
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//
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// Zone 7
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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//
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XintfRegs.XTIMING7.bit.XWRLEAD = 3;
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XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
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XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
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//
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// Zone read timing
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//
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XintfRegs.XTIMING7.bit.XRDLEAD = 3;
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XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
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XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
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//
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// double all Zone read/write lead/active/trail timing
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//
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XintfRegs.XTIMING7.bit.X2TIMING = 1;
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//
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// Zone will sample XREADY signal
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//
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XintfRegs.XTIMING7.bit.USEREADY = 1;
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XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
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//
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// Size must be either:
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// 0,1 = x32 or
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// 1,1 = x16 other values are reserved
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//
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XintfRegs.XTIMING7.bit.XSIZE = 3;
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//
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// Bank switching
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// Assume Zone 7 is slow, so add additional BCYC cycles
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// when ever switching from Zone 7 to another Zone.
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// This will help avoid bus contention.
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//
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XintfRegs.XBANK.bit.BANK = 7;
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XintfRegs.XBANK.bit.BCYC = 7;
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EDIS;
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//
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// Force a pipeline flush to ensure that the write to the last register
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// configured occurs before returning.
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//
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asm(" RPT #7 || NOP");
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if(setup.gpio_setup != 0)
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{
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_gpio_setup = setup.gpio_setup;
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//
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(*_gpio_setup)();
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//
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m_mode = DSP28335::XINTF::OPERATIONAL;
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m_status = true;
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//
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}//if
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//
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}//if
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//
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}//
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//
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} /* namespace DSP28335 */
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