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CCS-COMM_BOARD/main2.cpp

405 lines
12 KiB
C++

// Some comments about author
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "DSP2833x_Device.h"
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "DSP2833x_Examples.h"
// #include "Protocol/CAN.h"
// #include "Protocol/CAN_data.h"
// #include "Protocol/DigitalIO.h"
#include "Periphery.h"
#include "SinglePhaseDefaults.h"
#include "RUDRIVEFRAMEWORK/HeaderRUDRIVEFRAMEWORK.h"
#include "WEINBUS/HeaderWeinbus.h"
#include "PERIPHERY/PWMSInterace.h"
//Functions declarations
void idle_loop(void);
interrupt void cpu_timer0_isr(void);
interrupt void cpu_timer1_isr(void);
interrupt void canb_isr(void);
interrupt void canb_box_isr(void);
// Periphery periphery;
//----------------------------------------------------------------------------------------
DSP28335::SCISetup SCIbSetup;
DSP28335::SCIB scib(ScibRegs);
DSP28335::MeasureTimeInterval interval_measure(CpuTimer2);
// MODBUS RTU - PORT & HMI
MODBUSRTU::ModbusRTUTransceiverSetup modbus;
MODBUSRTU::ModbusRTUCRC crc;
MODBUSRTU::ModbusRTUTransceiver modbus_port(scib, interval_measure, crc);
WEINBUS::WeinbusSlave hmi(crc);
MODBUSRTU::ModbusRTUTransceiverConfiguration modbus_port_configuration;
// Registers to testing HMI interface
WEINBUS::REGISTER_32 test_hmi_float_reg_400 = WEINBUS::REGISTER_32(0);
WEINBUS::REGISTER_32 test_hmi_float_reg_401 = WEINBUS::REGISTER_32(0);
WEINBUS::REGISTER_32 test_hmi_float_reg_402 = WEINBUS::REGISTER_32(0);
WEINBUS::REGISTER_32 test_hmi_float_reg_403 = WEINBUS::REGISTER_32(0);
WEINBUS::REGISTER_32 test_hmi_float_reg_404 = WEINBUS::REGISTER_32(0);
//<>
void modify_hardware_setup(RUDRIVEFRAMEWORK::SinglePhaseSetup& setup);
void hardcode_pwm_configuration(PERIPHERY::PWMSInterfaceConfiguration& config);
void test_init_hmi_buffers();
void clear_array(uint16_t *pointer, uint16_t sizearray);
//----------------------------------------------------------------------------------------
volatile Uint16 infCounter = 0;
volatile Uint16 canISRcounter = 0;
volatile Uint16 canBoxISRcounter = 0;
volatile Uint16 testCounter = 0;
volatile bool init = true;
volatile bool startTX = false;
volatile bool update = false;
volatile bool sendRemote = false;
Uint16 modbusInit = 0;
int32 testVar = 0;
void main()
{
ServiceDog();
DisableDog();
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.XINT13 = &cpu_timer1_isr;
PieVectTable.ECAN0INTB = &canb_isr;
PieVectTable.ECAN1INTB = &canb_box_isr;
EDIS;
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, 150, 1000); // 1ms
ConfigCpuTimer(&CpuTimer1, 150, 5000); // 5ms
IER |= M_INT1; // Enable CPU Interrupt 1
IER |= M_INT9; // Enable CPU Interrupt 9
IER |= M_INT13; // Enable CPU Interrupt 13
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
PieCtrlRegs.PIEIER9.bit.INTx7 = 1; // from 5 to 8
PieCtrlRegs.PIEIER9.bit.INTx8 = 1;
// periphery.config();
//----------------------------------------------------------------------------------------
SCIbSetup.config.baudrate = SCIB_BAUDRATE_DEFAULT;
SCIbSetup.config.parity = SCIB_PARITY_DEFAULT;
SCIbSetup.config.stopbits = SCIB_STOPBITS_DEFAULT;
SCIbSetup.config.lenght = SCIB_LENGHT_DEFAULT;
SCIbSetup.gpio_setup = SCIB_GPIO_SETUP_DEFAULT;
modbus.gpio_re_de_setup = &DSP28335::GPIO::gpio_scib_re_de_setup;
modbus.gpio_driver_enable = &DSP28335::GPIO::gpio_scib_re_de_set;
modbus.gpio_receiver_enable = &DSP28335::GPIO::gpio_scib_re_de_clear;
scib.setup(SCIbSetup);
interval_measure.set_magic((Uint32)0);
interval_measure.reset();
modbus_port.setup(modbus);
//----------------------------------------------------------------------------------------
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// periphery.updateVersionFPGA();
//----------------------------------------------------------------------------------------
// MODBUS RTU
//
modbus_port_configuration.node_id = 0x5;
modbus_port_configuration.config.baudrate = DSP28335::BR9600;
modbus_port_configuration.config.parity = DSP28335::NO;
modbus_port_configuration.config.stopbits = DSP28335::ONE;
modbus_port_configuration.config.lenght = DSP28335::LEN8;
//
test_init_hmi_buffers();
modbus_port.configure(modbus_port_configuration);
clear_array((uint16_t *)hmi.rxStack, sizeof(hmi.rxStack)/sizeof(uint16_t));
clear_array((uint16_t *)hmi.txStack, sizeof(hmi.txStack)/sizeof(uint16_t));
modbus_port.setRXBuffer((uint16_t*)hmi.rxStack, &hmi.rxLength);
modbus_port.setTXBuffer((uint16_t*)hmi.txStack, &hmi.txLength);
// interval_measure.set_magic(19);
//----------------------------------------------------------------------------------------
CpuTimer0.RegsAddr->TCR.bit.TSS = 0;
CpuTimer1.RegsAddr->TCR.bit.TSS = 0;
idle_loop();
//
}//end main()
//
//
void idle_loop()
{
while (true)
{
infCounter++;
// periphery.initExternalModbus();
//
// MODBUS RTU HMI Service
//
if(modbus_port.compare_state(MODBUSRTU::BREAK))
{
modbus_port.port_reset();
//
}
else
{
modbus_port.execute();
hmi.execute();
//
}//if else
//<>
}//end while
}//end idle_loop()
interrupt void cpu_timer0_isr(void)
{
// periphery.processDigitalOutput();
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
}//end
interrupt void cpu_timer1_isr(){
CpuTimer1.InterruptCount++;
// periphery.processDigitalInput();
}
interrupt void canb_isr(void){
canISRcounter++;
CANGIF0_REG CANGIF0_SHADOW;
volatile Uint32 resetBit;
CANGIF0_SHADOW.all = ECanbRegs.CANGIF0.all;
if (CANGIF0_SHADOW.bit.WLIF0){
resetBit = 256;
ECanbRegs.CANGIF0.all = 256ul;
}
if (CANGIF0_SHADOW.bit.EPIF0){
ECanbRegs.CANGIF0.all = 528ul;
}
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;
}
interrupt void canb_box_isr(void){
canBoxISRcounter++;
// Just example
//
// volatile Uint32 boxNumberIsr;
// boxNumberIsr = ECanbRegs.CANGIF1.bit.MIV1;
// CANRMP_REG temp;
// temp.all = 0;
// temp.all = 1ul << 27;
// ECanbRegs.CANRMP.all = temp.all;
// MODBUS_COMM_CPU_Message27.mdh.all = ECanbMboxes.MBOX27.MDH.all;
// MODBUS_COMM_CPU_Message27.mdl.all = ECanbMboxes.MBOX27.MDL.all;
// temp.all = ECanbRegs.CANRMP.all;
// if (temp.bit.RMP25){
// temp.all = 1ul << 25;
// ECanbRegs.CANRMP.all = temp.all;
// MODBUS_COMM_CPU_Message25.mdh.all = ECanbMboxes.MBOX25.MDH.all;
// MODBUS_COMM_CPU_Message25.mdl.all = ECanbMboxes.MBOX25.MDL.all;
// }
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;
}
void test_init_hmi_buffers()
{
//
// hmi writeable registers
hmi.inputRegisters.set(WEINBUS::INPUTREGISTERS, 400);
hmi.inputRegisters.add( 0, &(float&)test_hmi_float_reg_400.f);
hmi.inputRegisters.add( 1, &(float&)test_hmi_float_reg_401.f);
hmi.inputRegisters.add( 2, &(float&)test_hmi_float_reg_402.f);
hmi.inputRegisters.add( 3, &(float&)test_hmi_float_reg_403.f);
hmi.inputRegisters.add( 4, &(float&)test_hmi_float_reg_404.f);
//
// hmi readable registers
hmi.outputRegisters.set(WEINBUS::OUTPUTREGISTERS, 400);
hmi.outputRegisters.add( 0 , &(float&)test_hmi_float_reg_400.f);
hmi.outputRegisters.add( 1, &(float&)test_hmi_float_reg_401.f);
hmi.outputRegisters.add( 2, &(float&)test_hmi_float_reg_402.f);
hmi.outputRegisters.add( 3, &(float&)test_hmi_float_reg_403.f);
hmi.outputRegisters.add( 4, &(float&)test_hmi_float_reg_404.f);
//
}//
//
void clear_array(uint16_t *pointer, uint16_t sizearray)
{
static uint16_t *p_array = 0;
static uint16_t size_array = 0;
p_array = pointer;
size_array = sizearray;
while(size_array--)
{
*p_array++ = 0;
}
//
}//
void modify_hardware_setup(RUDRIVEFRAMEWORK::SinglePhaseSetup& setup)
{
//
// SCIB - interface with monitor? RS485, MODBUS RTU
//
//setup.cpu.scib.config.baudrate = SCIB_BAUDRATE_DEFAULT;
//setup.cpu.scib.config.parity = SCIB_PARITY_DEFAULT;
//setup.cpu.scib.config.stopbits = SCIB_STOPBITS_DEFAULT;
//setup.cpu.scib.config.lenght = SCIB_LENGHT_DEFAULT;
//setup.cpu.scib.gpio_setup = SCIB_GPIO_SETUP_DEFAULT;
//
// SCIC - internal interface
//
//setup.cpu.scic.config.baudrate = SCIC_BAUDRATE_DEFAULT;
//setup.cpu.scic.config.parity = SCIC_PARITY_DEFAULT;
//setup.cpu.scic.config.stopbits = SCIC_STOPBITS_DEFAULT;
//setup.cpu.scic.config.lenght = SCIC_LENGHT_DEFAULT;
//setup.cpu.scic.gpio_setup = SCIC_GPIO_SETUP_DEFAULT;
//
// CPU Timers
//
//setup.cpu.cpu_timers.frequency = 150.0; //150MHz
//setup.cpu.cpu_timers.period = 1000.0; //1000us
//
// EPWM
//
// setup.cpu.epwm.parameters.fpwm = 750.0; //Hz
//setup.cpu.epwm.parameters.pulse_sync = 1.0e-6; //s
//setup.cpu.epwm.parameters.pulse_adc_soc = 32.0e-6; //s
//setup.cpu.epwm.parameters.adc_soc_offset = FP_ZERO; //relative
// setup.cpu.epwm.parameters.adc_soc_quantity = 3;
//setup.cpu.epwm.gpio_setup = &DSP28335::GPIO::gpio_epwm_setup;
//
// XINTF
//
//setup.cpu.xintf.gpio_setup = &DSP28335::GPIO::gpio_xintf_16bit_setup;
//
// ECANA
//
//setup.cpu.ecana.gpio_setup = &DSP28335::GPIO::gpio_cana_setup;
//
// ECANB
//
//setup.cpu.ecanb.gpio_setup = &DSP28335::GPIO::gpio_canb_setup;
//
// EQEP
//
//setup.cpu.eqep1.gpio_setup = &DSP28335::GPIO::gpio_eqep_setup;
//
// Discrete Outputs
//
//setup.cpu.dout.gpio_setup = &DSP28335::GPIO::gpio_dicrete_outputs_setup;
//
// Analog Faults
//
//setup.periphery.analog_faults.p_gpio_analog_fault_setup = &DSP28335::GPIO::gpio_analog_fault_setup;
//setup.periphery.analog_faults.p_analog_fault_read = &DSP28335::GPIO::gpio_analog_fault_read;
}//
void hardcode_pwm_configuration(PERIPHERY::PWMSInterfaceConfiguration& config)
{
config.pwm_frequency = SINGLE_PHASE_PWM_FREQUENCY;
config.adc_isr_quantity = SINGLE_PHASE_ADC_ISR_QUANTITY;
config.adc_isr_offset_relative = SINGLE_PHASE_ADC_ISR_OFFSET_RELATIVE;
config.cascade_quantity = SINGLE_PHASE_CASCADE_QUANTITY;
config.cell_quantity = SINGLE_PHASE_CELL_QUANTITY;
config.cell_quantity_in_cascade[0] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_00;
config.cell_quantity_in_cascade[1] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_01;
config.cell_quantity_in_cascade[2] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_02;
config.cell_quantity_in_cascade[3] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_03;
config.cell_quantity_in_cascade[4] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_04;
config.cell_quantity_in_cascade[5] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_05;
config.cell_quantity_in_cascade[6] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_06;
config.cell_quantity_in_cascade[7] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_07;
config.cell_quantity_in_cascade[8] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_08;
config.cell_quantity_in_cascade[9] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_09;
config.cell_quantity_in_cascade[10] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_10;
config.cell_quantity_in_cascade[11] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_11;
config.cell_quantity_in_cascade[12] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_12;
config.cell_quantity_in_cascade[13] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_13;
config.cell_quantity_in_cascade[14] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_14;
config.cell_quantity_in_cascade[15] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_15;
config.cell_quantity_in_cascade[16] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_16;
config.cell_quantity_in_cascade[17] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_17;
//
}//
//