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188 lines
7.8 KiB
C++
188 lines
7.8 KiB
C++
4 weeks ago
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/*
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* ADC.cpp
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*
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* Author: Aleksey Gerasimenko
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* gerasimenko.aleksey.n@gmail.com
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*/
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#include "DSP28335/ADC.h"
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namespace DSP28335
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{
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//CONSTRUCTOR
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ADC::ADC():
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DSP28335::CPUBase(),
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m_status(false)
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//
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{}//end CONSTRUCTOR
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//
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void DSP28335::ADC::setup()
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{
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if(m_mode == DSP28335::ADC::UNDEFINED)
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{
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//--- Configure the other ADC registers
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AdcRegs.ADCREFSEL.bit.REF_SEL = 0; // ADC reference, 0=internal, 1=external
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//--- Power-up the ADC
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//AdcRegs.ADCTRL3.all = 0x00EC; // Power-up reference and main ADC
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//AdcRegs.ADCTRL3.all = 0x00F4; // Power-up reference and main ADC /20
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//AdcRegs.ADCTRL3.all = 0x00EE; // Power-up reference and main ADC /14
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//AdcRegs.ADCTRL3.all = 0x00EA; // Power-up reference and main ADC /10
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//AdcRegs.ADCTRL3.all = 0x00E8; // Power-up reference and main ADC /8
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//AdcRegs.ADCTRL3.all = 0x00E4; // Power-up reference and main ADC /4
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// bit 15-8 0's: reserved
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// bit 7-6 11: ADCBGRFDN, reference power, 00=off, 11=on
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// bit 5 1: ADCPWDN, main ADC power, 0=off, 1=on
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// bit 4-1 0110: ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
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// bit 0 0: SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
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AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0008; // bit 4-1 0110: ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
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AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0000; // bit 0 0: SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
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AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x0003; // bit 7-6 11: ADCBGRFDN, reference power, 00=off, 11=on
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AdcRegs.ADCTRL3.bit.ADCPWDN = 0x0001; // bit 5 1: ADCPWDN, main ADC power, 0=off, 1=on
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DELAY_US(5000); // Wait 5 ms before using the ADC
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//AdcRegs.ADCTRL1.all = 0x0710;
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// bit 15 0: reserved
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// bit 14 0: RESET, 0=no action, 1=reset ADC
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// bit 13-12 00: SUSMOD, 00=ignore emulation suspend
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// bit 11-8 0111: ACQ_PS (Acquisition), 0111 = 8 x ADCCLK
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// bit 7 0: CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2
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// bit 6 0: CONT_RUN, 0=start/stop mode, 1=continuous run
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// bit 5 0: SEQ_OVRD, 0=disabled, 1=enabled
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// bit 4 1: SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer
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// bit 3-0 0000: reserved
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AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascaded mode
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AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // Disable Sequencer override
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AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0; // Start-stop mode
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AdcRegs.ADCTRL1.bit.CPS = 0x0; // Core Clock Prescaler = 1 (ADCCLK=Fclk/1)
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AdcRegs.ADCTRL1.bit.ACQ_PS = 0x2; // Acqusition window size
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AdcRegs.ADCTRL1.bit.SUSMOD = 0x0; // Emulation-suspend mode
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//AdcRegs.ADCTRL2.all = 0x0900;
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// bit 15 0: ePWM_SOCB_SEQ, 0=no action
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// bit 14 0: RST_SEQ1, 0=no action
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// bit 13 0: SOC_SEQ1, 0=clear any pending SOCs
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// bit 12 0: reserved
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// bit 11 1: INT_ENA_SEQ1, 1=enable interrupt
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// bit 10 0: INT_MOD_SEQ1, 0=int on every SEQ1 conv
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// bit 9 0: reserved
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// bit 8 1: ePWM_SOCA_SEQ1, 1=SEQ1 start from ePWM_SOCA trigger
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// bit 7 0: EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin
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// bit 6 0: RST_SEQ2, 0=no action
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// bit 5 0: SOC_SEQ2, no effect in cascaded mode
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// bit 4 0: reserved
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// bit 3 0: INT_ENA_SEQ2, 0=int disabled
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// bit 2 0: INT_MOD_SEQ2, 0=int on every other SEQ2 conv
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// bit 1 0: reserved
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// bit 0 0: ePWM_SOCB_SEQ2, 0=no action
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AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 0x0; // ePWM SOCB enable bit for SEQ2
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AdcRegs.ADCTRL2.bit.INT_MOD_SEQ2 = 0x0; // SEQ2 interrupt mode
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AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 = 0x0; // SEQ2 interrupt enable
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AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 0x0; // SOC SEQ2
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AdcRegs.ADCTRL2.bit.RST_SEQ2 = 0x0; // Reset SEQ2
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AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1 = 0x0; // external SOC SEQ1
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AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 0x0; // ePWM SOCB enable bit for SEQ1
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AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; // SEQ1 interrupt mode
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AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // SEQ1 interrupt enable
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AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x0; // SOC SEQ1
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1; // Reset SEQ1
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AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 0x0; // ePWM SOCB enable for cascaded sequencer
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AdcRegs.ADCMAXCONV.all = 15;
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// bit 15-7 0's: reserved
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// bit 6-4 000: MAX_CONV2 value
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// bit 3-0 0000: MAX_CONV1 value (0 means 1 conversion)
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// Since we are only doing 1 conversion in the sequence, we only need to
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// configure the ADCCHSELSEQ1 register, and only the CONV00 field. All
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// other channel selection fields are don't cares in this example.
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//AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // Convert Channel 0
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA3 as 1st SEQ conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA2 as 2nd SEQ conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3nd SEQ conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup ADCINA2 as 4nd SEQ conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup ADCINA3 as 5st SEQ conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup ADCINA2 as 6nd SEQ conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup ADCINA2 as 7nd SEQ conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup ADCINA2 as 8nd SEQ conv.
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AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8; // Setup ADCINA3 as 9st SEQ conv.
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AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9; // Setup ADCINA2 as 10nd SEQ conv.
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AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xA; // Setup ADCINA2 as 11nd SEQ conv.
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AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xB; // Setup ADCINA2 as 12nd SEQ conv.
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AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xC; // Setup ADCINA3 as 13st SEQ conv.
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AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xD; // Setup ADCINA2 as 14nd SEQ conv.
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AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xE; // Setup ADCINA2 as 15nd SEQ conv.
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AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0xF; // Setup ADCINA2 as 16nd SEQ conv.
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//
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//
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//
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m_mode = DSP28335::ADC::OPERATIONAL;
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//
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}//end if
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//
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}//end
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//.TI.ramfunc
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// #pragma CODE_SECTION("ramfuncs");
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bool DSP28335::ADC::is_ready()
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{
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return m_status;
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//
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}//end
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//
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// #pragma CODE_SECTION("ramfuncs");
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void DSP28335::ADC::clear_status()
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{
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m_status = false;
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//
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}//end
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// #pragma CODE_SECTION("ramfuncs");
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void DSP28335::ADC::sw_soc_seq1()
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{
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if(m_mode == DSP28335::ADC::OPERATIONAL)
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{
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AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
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//
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}//if
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//
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}//end
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//
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// #pragma CODE_SECTION("ramfuncs");
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void DSP28335::ADC::sw_soc_seq2()
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{
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if(m_mode == DSP28335::ADC::OPERATIONAL)
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{
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AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 1;
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//
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}//if
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//
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}//end
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// #pragma CODE_SECTION("ramfuncs");
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void DSP28335::ADC::interrupt_ack()
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{
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m_status = true;
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//AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
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//PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
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// Reinitialize for next ADC sequence
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
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AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
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//
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}//end
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//
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} /* namespace DSP28335 */
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