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// TI File $Revision: /main/2 $
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// Checkin $Date: March 22, 2007 10:40:22 $
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//###########################################################################
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//
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// FILE: DSP2833x_I2c.h
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//
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// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
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// Register Bit Definitions.
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//
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//###########################################################################
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// $TI Release: 2833x/2823x Header Files V1.32 $
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// $Release Date: June 28, 2010 $
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// $Copyright:
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// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef DSP2833x_I2C_H
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#define DSP2833x_I2C_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// I2C interrupt vector register bit definitions
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//
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struct I2CISRC_BITS { // bits description
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Uint16 INTCODE:3; // 2:0 Interrupt code
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Uint16 rsvd1:13; // 15:3 reserved
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};
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union I2CISRC_REG {
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Uint16 all;
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struct I2CISRC_BITS bit;
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};
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//
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// I2C interrupt mask register bit definitions
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//
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struct I2CIER_BITS { // bits description
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Uint16 ARBL:1; // 0 Arbitration lost interrupt
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Uint16 NACK:1; // 1 No ack interrupt
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Uint16 ARDY:1; // 2 Register access ready interrupt
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Uint16 RRDY:1; // 3 Recieve data ready interrupt
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Uint16 XRDY:1; // 4 Transmit data ready interrupt
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Uint16 SCD:1; // 5 Stop condition detection
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Uint16 AAS:1; // 6 Address as slave
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Uint16 rsvd:9; // 15:7 reserved
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};
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union I2CIER_REG {
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Uint16 all;
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struct I2CIER_BITS bit;
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};
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//
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// I2C status register bit definitions
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//
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struct I2CSTR_BITS { // bits description
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Uint16 ARBL:1; // 0 Arbitration lost interrupt
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Uint16 NACK:1; // 1 No ack interrupt
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Uint16 ARDY:1; // 2 Register access ready interrupt
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Uint16 RRDY:1; // 3 Recieve data ready interrupt
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Uint16 XRDY:1; // 4 Transmit data ready interrupt
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Uint16 SCD:1; // 5 Stop condition detection
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Uint16 rsvd1:2; // 7:6 reserved
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Uint16 AD0:1; // 8 Address Zero
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Uint16 AAS:1; // 9 Address as slave
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Uint16 XSMT:1; // 10 XMIT shift empty
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Uint16 RSFULL:1; // 11 Recieve shift full
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Uint16 BB:1; // 12 Bus busy
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Uint16 NACKSNT:1; // 13 A no ack sent
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Uint16 SDIR:1; // 14 Slave direction
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Uint16 rsvd2:1; // 15 reserved
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};
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union I2CSTR_REG {
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Uint16 all;
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struct I2CSTR_BITS bit;
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};
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//
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// I2C mode control register bit definitions
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//
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struct I2CMDR_BITS { // bits description
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Uint16 BC:3; // 2:0 Bit count
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Uint16 FDF:1; // 3 Free data format
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Uint16 STB:1; // 4 Start byte
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Uint16 IRS:1; // 5 I2C Reset not
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Uint16 DLB:1; // 6 Digital loopback
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Uint16 RM:1; // 7 Repeat mode
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Uint16 XA:1; // 8 Expand address
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Uint16 TRX:1; // 9 Transmitter/reciever
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Uint16 MST:1; // 10 Master/slave
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Uint16 STP:1; // 11 Stop condition
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Uint16 rsvd1:1; // 12 reserved
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Uint16 STT:1; // 13 Start condition
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Uint16 FREE:1; // 14 Emulation mode
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Uint16 NACKMOD:1; // 15 No Ack mode
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};
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union I2CMDR_REG {
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Uint16 all;
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struct I2CMDR_BITS bit;
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};
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//
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// I2C extended mode control register bit definitions
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//
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struct I2CEMDR_BITS { // bits description
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Uint16 BCM:1; // 0 Backward compatibility mode
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Uint16 rsvd:15; // 15 reserved
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};
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union I2CEMDR_REG {
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Uint16 all;
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struct I2CEMDR_BITS bit;
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};
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//
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// I2C pre-scaler register bit definitions
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//
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struct I2CPSC_BITS { // bits description
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Uint16 IPSC:8; // 7:0 pre-scaler
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Uint16 rsvd1:8; // 15:8 reserved
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};
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union I2CPSC_REG {
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Uint16 all;
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struct I2CPSC_BITS bit;
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};
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//
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// TX FIFO control register bit definitions
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//
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struct I2CFFTX_BITS { // bits description
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Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
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Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
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Uint16 TXFFINTCLR:1; // 6 FIFO clear
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Uint16 TXFFINT:1; // 7 FIFO interrupt flag
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Uint16 TXFFST:5; // 12:8 FIFO level status
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Uint16 TXFFRST:1; // 13 FIFO reset
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Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
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Uint16 rsvd1:1; // 15 reserved
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};
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union I2CFFTX_REG {
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Uint16 all;
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struct I2CFFTX_BITS bit;
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};
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//
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// RX FIFO control register bit definitions
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//
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struct I2CFFRX_BITS { // bits description
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Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
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Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
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Uint16 RXFFINTCLR:1; // 6 FIFO clear
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Uint16 RXFFINT:1; // 7 FIFO interrupt flag
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Uint16 RXFFST:5; // 12:8 FIFO level
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Uint16 RXFFRST:1; // 13 FIFO reset
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Uint16 rsvd1:2; // 15:14 reserved
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};
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union I2CFFRX_REG {
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Uint16 all;
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struct I2CFFRX_BITS bit;
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};
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struct I2C_REGS {
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Uint16 I2COAR; // Own address register
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union I2CIER_REG I2CIER; // Interrupt enable
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union I2CSTR_REG I2CSTR; // Interrupt status
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Uint16 I2CCLKL; // Clock divider low
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Uint16 I2CCLKH; // Clock divider high
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Uint16 I2CCNT; // Data count
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Uint16 I2CDRR; // Data recieve
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Uint16 I2CSAR; // Slave address
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Uint16 I2CDXR; // Data transmit
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union I2CMDR_REG I2CMDR; // Mode
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union I2CISRC_REG I2CISRC; // Interrupt source
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union I2CEMDR_REG I2CEMDR; // Extended Mode
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union I2CPSC_REG I2CPSC; // Pre-scaler
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Uint16 rsvd2[19]; // reserved
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union I2CFFTX_REG I2CFFTX; // Transmit FIFO
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union I2CFFRX_REG I2CFFRX; // Recieve FIFO
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};
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//
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// External References & Function Declarations
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//
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extern volatile struct I2C_REGS I2caRegs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_I2C_H definition
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//
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// End of file
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//
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