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367 lines
13 KiB
C
367 lines
13 KiB
C
4 weeks ago
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//###########################################################################
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//
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// FILE: DSP2833x_DMA.h
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//
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// TITLE: DSP2833x DMA Module Register Bit Definitions.
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//
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//###########################################################################
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// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
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// $Release Date: November 1, 2016 $
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// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
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// http://www.ti.com/ ALL RIGHTS RESERVED $
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//###########################################################################
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#ifndef DSP2833x_DMA_H
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#define DSP2833x_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// Channel MODE register bit definitions
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//
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struct MODE_BITS { // bits description
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Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W):
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// 0 no interrupt
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// 1 SEQ1INT & ADCSYNC
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// 2 SEQ2INT
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// 3 XINT1
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// 4 XINT2
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// 5 XINT3
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// 6 XINT4
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// 7 XINT5
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// 8 XINT6
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// 9 XINT7
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// 10 XINT13
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// 11 TINT0
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// 12 TINT1
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// 13 TINT2
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// 14 MXEVTA & MXSYNCA
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// 15 MREVTA & MRSYNCA
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// 16 MXEVTB & MXSYNCB
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// 17 MREVTB & MRSYNCB
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// 18 ePWM1SOCA
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// 19 ePWM1SOCB
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// 20 ePWM2SOCA
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// 21 ePWM2SOCB
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// 22 ePWM3SOCA
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// 23 ePWM3SOCB
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// 24 ePWM4SOCA
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// 25 ePWM4SOCB
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// 26 ePWM5SOCA
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// 27 ePWM5SOCB
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// 28 ePWM6SOCA
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// 29 ePWM6SOCB
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// 30:31 no interrupt
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Uint16 rsvd1:2; // 6:5 (R=0:0)
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Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W):
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// 0 overflow interrupt disabled
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// 1 overflow interrupt enabled
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Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W):
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// 0 peripheral interrupt disabled
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// 1 peripheral interrupt enabled
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Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W):
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// 0 generate interrupt at beginning of new
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// transfer
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// 1 generate interrupt at end of transfer
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Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W):
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// 0 only interrupt event triggers single
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// burst transfer
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// 1 first interrupt triggers burst,
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// continue until transfer count is zero
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Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W):
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// 0 stop when transfer count is zero
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// 1 re-initialize when transfer count is
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// zero
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Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W):
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// 0 ignore selected interrupt sync signal
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// 1 enable selected interrupt sync signal
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Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W):
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// 0 sync signal controls source wrap
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// counter
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// 1 sync signal controls destination wrap
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// counter
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Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W):
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// 0 16-bit data transfer size
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// 1 32-bit data transfer size
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Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W):
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// 0 channel interrupt disabled
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// 1 channel interrupt enabled
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};
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union MODE_REG {
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Uint16 all;
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struct MODE_BITS bit;
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};
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//
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// Channel CONTROL register bit definitions
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//
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struct CONTROL_BITS { // bits description
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Uint16 RUN:1; // 0 Run Bit (R=0/W=1)
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Uint16 HALT:1; // 1 Halt Bit (R=0/W=1)
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Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1)
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Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1)
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Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1)
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Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1)
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Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1)
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Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1)
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Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R):
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// 0 no interrupt pending
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// 1 interrupt pending
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Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R):
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// 0 no sync pending
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// 1 sync pending
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Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R):
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// 0 no sync error
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// 1 sync error detected
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Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R):
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// 0 no transfer in progress or pending
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// 1 transfer in progress or pending
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Uint16 BURSTSTS:1; // 12 Burst Status Bit (R):
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// 0 no burst in progress or pending
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// 1 burst in progress or pending
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Uint16 RUNSTS:1; // 13 Run Status Bit (R):
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// 0 channel not running or halted
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// 1 channel running
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Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R)
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// 0 no overflow event
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// 1 overflow event
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Uint16 rsvd1:1; // 15 (R=0)
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};
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union CONTROL_REG {
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Uint16 all;
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struct CONTROL_BITS bit;
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};
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//
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// DMACTRL register bit definitions
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//
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struct DMACTRL_BITS { // bits description
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Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1)
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Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1)
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Uint16 rsvd1:14; // 15:2 (R=0:0)
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};
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union DMACTRL_REG {
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Uint16 all;
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struct DMACTRL_BITS bit;
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};
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//
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// DEBUGCTRL register bit definitions
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//
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struct DEBUGCTRL_BITS { // bits description
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Uint16 rsvd1:15; // 14:0 (R=0:0)
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Uint16 FREE:1; // 15 Debug Mode Bit (R/W):
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// 0 halt after current read-write operation
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// 1 continue running
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};
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union DEBUGCTRL_REG {
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Uint16 all;
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struct DEBUGCTRL_BITS bit;
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};
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//
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// PRIORITYCTRL1 register bit definitions
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//
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struct PRIORITYCTRL1_BITS { // bits description
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Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W):
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// 0 same priority as all other channels
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// 1 highest priority channel
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Uint16 rsvd1:15; // 15:1 (R=0:0)
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};
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union PRIORITYCTRL1_REG {
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Uint16 all;
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struct PRIORITYCTRL1_BITS bit;
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};
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//
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// PRIORITYSTAT register bit definitions:
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//
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struct PRIORITYSTAT_BITS { // bits description
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Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R):
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// 0,0,0 no channel active
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// 0,0,1 Ch1 channel active
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// 0,1,0 Ch2 channel active
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// 0,1,1 Ch3 channel active
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// 1,0,0 Ch4 channel active
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// 1,0,1 Ch5 channel active
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// 1,1,0 Ch6 channel active
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Uint16 rsvd1:1; // 3 (R=0)
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Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R):
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// 0,0,0 no channel active & interrupted by Ch1
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// 0,0,1 cannot occur
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// 0,1,0 Ch2 was active and interrupted by Ch1
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// 0,1,1 Ch3 was active and interrupted by Ch1
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// 1,0,0 Ch4 was active and interrupted by Ch1
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// 1,0,1 Ch5 was active and interrupted by Ch1
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// 1,1,0 Ch6 was active and interrupted by Ch1
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Uint16 rsvd2:9; // 15:7 (R=0:0)
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};
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union PRIORITYSTAT_REG {
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Uint16 all;
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struct PRIORITYSTAT_BITS bit;
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};
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//
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// Burst Size
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//
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struct BURST_SIZE_BITS { // bits description
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Uint16 BURSTSIZE:5; // 4:0 Burst transfer size
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Uint16 rsvd1:11; // 15:5 reserved
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};
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union BURST_SIZE_REG {
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Uint16 all;
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struct BURST_SIZE_BITS bit;
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};
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//
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// Burst Count
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//
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struct BURST_COUNT_BITS { // bits description
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Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size
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Uint16 rsvd1:11; // 15:5 reserved
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};
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union BURST_COUNT_REG {
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Uint16 all;
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struct BURST_COUNT_BITS bit;
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};
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//
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// DMA Channel Registers:
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//
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struct CH_REGS {
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union MODE_REG MODE; // Mode Register
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union CONTROL_REG CONTROL; // Control Register
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union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
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union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
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//
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// Source Burst Step Register
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//
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int16 SRC_BURST_STEP;
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//
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// Destination Burst Step Register
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//
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int16 DST_BURST_STEP;
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Uint16 TRANSFER_SIZE; // Transfer Size Register
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Uint16 TRANSFER_COUNT; // Transfer Count Register
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//
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// Source Transfer Step Register
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//
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int16 SRC_TRANSFER_STEP;
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//
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// Destination Transfer Step Register
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//
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int16 DST_TRANSFER_STEP;
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Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
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Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
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int16 SRC_WRAP_STEP; // Source Wrap Step Register
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//
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// Destination Wrap Size Register
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//
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Uint16 DST_WRAP_SIZE;
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//
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// Destination Wrap Count Register
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//
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Uint16 DST_WRAP_COUNT;
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//
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// Destination Wrap Step Register
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//
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int16 DST_WRAP_STEP;
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//
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// Source Begin Address Shadow Register
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//
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Uint32 SRC_BEG_ADDR_SHADOW;
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//
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// Source Address Shadow Register
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//
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Uint32 SRC_ADDR_SHADOW;
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//
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// Source Begin Address Active Register
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//
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Uint32 SRC_BEG_ADDR_ACTIVE;
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//
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// Source Address Active Register
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//
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Uint32 SRC_ADDR_ACTIVE;
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//
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// Destination Begin Address Shadow Register
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//
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Uint32 DST_BEG_ADDR_SHADOW;
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//
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// Destination Address Shadow Register
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//
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Uint32 DST_ADDR_SHADOW;
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//
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// Destination Begin Address Active Register
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//
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Uint32 DST_BEG_ADDR_ACTIVE;
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//
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// Destination Address Active Register
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//
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Uint32 DST_ADDR_ACTIVE;
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};
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//
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// DMA Registers
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//
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struct DMA_REGS {
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union DMACTRL_REG DMACTRL; // DMA Control Register
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union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
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Uint16 rsvd0; // reserved
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Uint16 rsvd1; //
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union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
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Uint16 rsvd2; //
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union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
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Uint16 rsvd3[25]; //
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struct CH_REGS CH1; // DMA Channel 1 Registers
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struct CH_REGS CH2; // DMA Channel 2 Registers
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struct CH_REGS CH3; // DMA Channel 3 Registers
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struct CH_REGS CH4; // DMA Channel 4 Registers
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struct CH_REGS CH5; // DMA Channel 5 Registers
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struct CH_REGS CH6; // DMA Channel 6 Registers
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};
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//
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// External References & Function Declarations
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//
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extern volatile struct DMA_REGS DmaRegs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_DMA_H definition
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//
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// End of file
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//
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