CCS-COMM_BOARD/Protocol/CAN.cpp

#include "CAN.h"
#include <cstddef>

CAN::CAN(){

}

void CAN::initGpio(CAN_VARIANT canVarinat){
    if(canVarinat == CANA) InitECanaGpio();
    else if (canVarinat == CANB) InitECanbGpio();
}

void CAN::config(CAN_VARIANT canVarinat, Uint16 baudrate){
    if (canVarinat == CANA){
		EALLOW;
		SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1;
		EDIS;
		p_CanRegs_ = &ECanaRegs;
		p_CanMBoxes_ = &ECanaMboxes;
	}
	else if (canVarinat == CANB){
		EALLOW;
		SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1;
		EDIS;
		p_CanRegs_ = &ECanbRegs;
		p_CanMBoxes_ = &ECanbMboxes;
	}
	else { return; }

    //
    // Create a shadow register structure for the CAN control registers. This 
    // is needed, since only 32-bit access is allowed to these registers. 
    // 16-bit access to these registers could potentially corrupt the register
    // contents or return false data. This is especially true while writing 
    // to/reading from a bit (or group of bits) among bits 16 - 31
    //
    // struct ECAN_REGS ECanShadow;

    EALLOW;		// EALLOW enables access to protected bits

    //
    // Configure eCAN RX and TX pins for CAN operation using eCAN regs
    //
    CanShadow_.CANTIOC.all = p_CanRegs_->CANTIOC.all;
    CanShadow_.CANTIOC.bit.TXFUNC = 1;
    p_CanRegs_->CANTIOC.all = CanShadow_.CANTIOC.all;

    CanShadow_.CANRIOC.all = p_CanRegs_->CANRIOC.all;
    CanShadow_.CANRIOC.bit.RXFUNC = 1;
    p_CanRegs_->CANRIOC.all = CanShadow_.CANRIOC.all;

    //
    // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
    // HECC mode also enables time-stamping feature
    //
    CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
    CanShadow_.CANMC.bit.SCB = 1;
    p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;

    //
    // Initialize all bits of 'Master Control Field' to zero
    // Some bits of MSGCTRL register come up in an unknown state. For proper 
    // operation, all bits (including reserved bits) of MSGCTRL must be 
    // initialized to zero
    p_CanMBoxes_->MBOX0.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX1.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX2.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX3.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX4.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX5.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX6.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX7.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX8.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX9.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX10.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX11.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX12.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX13.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX14.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX15.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX16.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX17.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX18.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX19.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX20.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX21.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX22.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX23.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX24.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX25.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX26.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX27.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX28.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX29.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX30.MSGCTRL.all = 0x00000000;
    p_CanMBoxes_->MBOX31.MSGCTRL.all = 0x00000000;
    //
    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution.
    //
    p_CanRegs_->CANTA.all	= 0xFFFFFFFF;       // Clear all TAn bits

    p_CanRegs_->CANRMP.all = 0xFFFFFFFF;      // Clear all RMPn bits

    p_CanRegs_->CANGIF0.all = 0xFFFFFFFF;     // Clear all interrupt flag bits
    p_CanRegs_->CANGIF1.all = 0xFFFFFFFF;

    //
    // Configure bit timing parameters for eCANA
    //
    CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
    CanShadow_.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;

    CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
    CanShadow_.CANMC.bit.DBO = 1 ;            // Set DBO = 1
    p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;

    CanShadow_.CANES.all = p_CanRegs_->CANES.all;   //todo  Что за строка?

    do { CanShadow_.CANES.all = p_CanRegs_->CANES.all; }
    while(CanShadow_.CANES.bit.CCE != 1 );  	// Wait for CCE bit to be set

    CanShadow_.CANBTC.all = 0;

    // The following block for all 150 MHz SYSCLKOUT 
    // (75 MHz CAN clock) - default. Bit rate = 1 Mbps / 500 kbps / 250 kbps / 100 kbps
    //
    
    switch (baudrate) {
        case 1000:
            CanShadow_.CANBTC.bit.BRPREG = 4;
            CanShadow_.CANBTC.bit.TSEG2REG = 3;
            CanShadow_.CANBTC.bit.TSEG1REG = 9;
        break;

        case 500:
            CanShadow_.CANBTC.bit.BRPREG = 9;
            CanShadow_.CANBTC.bit.TSEG2REG = 3;
            CanShadow_.CANBTC.bit.TSEG1REG = 9;
        break;

        case 250:
            CanShadow_.CANBTC.bit.BRPREG = 19;
            CanShadow_.CANBTC.bit.TSEG2REG = 3;
            CanShadow_.CANBTC.bit.TSEG1REG = 9;
        break;

        case 100:
        CanShadow_.CANBTC.bit.BRPREG = 49;
        CanShadow_.CANBTC.bit.TSEG2REG = 3;
        CanShadow_.CANBTC.bit.TSEG1REG = 9;
        break;

        default: return;
    }

    CanShadow_.CANBTC.bit.SAM = 1;
    p_CanRegs_->CANBTC.all = CanShadow_.CANBTC.all;

    CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
    CanShadow_.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;

    CanShadow_.CANES.all = p_CanRegs_->CANES.all;

    do { CanShadow_.CANES.all = p_CanRegs_->CANES.all; }
    while(CanShadow_.CANES.bit.CCE != 0 ); // Wait for CCE bit to be  cleared

    //
    // Disable all Mailboxes
    //
    p_CanRegs_->CANME.all = 0;		// Required before writing the MSGIDs

    CanShadow_.CANTRR.all = p_CanRegs_->CANTRR.all;
    CanShadow_.CANTRR.bit.TRR0 = 1;
    p_CanRegs_->CANTRR.all  = CanShadow_.CANTRR.all;

    CanShadow_.CANTRS.all = p_CanRegs_->CANTRS.all;

    do {CanShadow_.CANTRS.all = p_CanRegs_->CANTRS.all;}
    while(CanShadow_.CANTRS.bit.TRS0 != 0);            // Wait for TRS bit to be cleared

    //
    // Debug feature
    // Configure the eCAN for self test mode.
    //
    CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
    CanShadow_.CANMC.bit.STM = 1;      // Configure CAN for self-test mode
    p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;

    EDIS;
}


void CAN::configTxMBoxes(){

    // Write to the MSGID field
    p_CanMBoxes_->MBOX1.MSGID.all = 0x0;    // IDE-0, AME-0, AAM-0
    p_CanMBoxes_->MBOX1.MSGID.bit.STDMSGID = 0xAAA;

    p_CanMBoxes_->MBOX1.MSGCTRL.bit.DLC = 8;    // Data length in bytes (0-8)
    p_CanMBoxes_->MBOX1.MSGCTRL.bit.RTR = 0;    // Remote Transmission Request

    CanShadow_.CANMD.all = p_CanRegs_->CANMD.all;
    CanShadow_.CANMD.bit.MD1 = 0;                      // Mailbox direction - transmit
    p_CanRegs_->CANMD.all = CanShadow_.CANMD.all;

    CanShadow_.CANME.all = p_CanRegs_->CANME.all;
    CanShadow_.CANME.bit.ME1 = 1;
    p_CanRegs_->CANME.all = CanShadow_.CANME.all;
}

void CAN::configRxMBoxes(){

    // Write to the MSGID field
    p_CanMBoxes_->MBOX25.MSGID.all = 0x0;
    p_CanMBoxes_->MBOX25.MSGID.bit.STDMSGID = 0xAAA;

    // Write to DLC field in Master Control reg
    p_CanMBoxes_->MBOX25.MSGCTRL.bit.DLC = 8;
    p_CanMBoxes_->MBOX25.MSGCTRL.bit.RTR = 0;

    //
    // Configure Mailbox under test as a Receive mailbox
    //
    CanShadow_.CANMD.all = p_CanRegs_->CANMD.all;
    CanShadow_.CANMD.bit.MD25 = 1;
    p_CanRegs_->CANMD.all = CanShadow_.CANMD.all;

    // Overwrite protection
    // CanShadow_.CANOPC.all = p_CanRegs_->CANOPC.all;
    // CanShadow_.CANOPC.bit.OPC1 = 1;                    // Should be one more mailbox to store 'overflow' messages
    // p_CanRegs_->CANOPC.all = CanShadow_.CANOPC.all;

    // Enable Mailbox
    CanShadow_.CANME.all = p_CanRegs_->CANME.all;
    CanShadow_.CANME.bit.ME25 = 1;
    p_CanRegs_->CANME.all = CanShadow_.CANME.all;

    // Write to the mailbox RAM field
    p_CanMBoxes_->MBOX25.MDL.all = 0x55555555;
    p_CanMBoxes_->MBOX25.MDH.all = 0x55555555;
}

void CAN::transmitMsg(Uint16 boxNumber){
    Uint32 mboxControl(0);
    mboxControl = 1ul << boxNumber;
    volatile struct MBOX* p_MailBox(NULL);
    p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;

    p_MailBox->MDH.all = 0x0;
    p_MailBox->MDL.all = 0x0;

    p_MailBox->MDH.all = 0xCCDD;
    p_MailBox->MDL.all = 0xAABB;

    CanShadow_.CANTRS.all = 0;
    CanShadow_.CANTRS.all |= mboxControl;   // Set TRS for mailbox under test
    p_CanRegs_->CANTRS.all = CanShadow_.CANTRS.all;

    do { CanShadow_.CANTA.all = p_CanRegs_->CANTA.all; }
    while((CanShadow_.CANTA.all & mboxControl) == 0 );// Wait for TA1 bit to be set

    CanShadow_.CANTA.all = 0;
    CanShadow_.CANTA.all |= mboxControl;    // Clear TA1
    p_CanRegs_->CANTA.all = CanShadow_.CANTA.all;
}

void CAN::receiveMsg(){

}