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// TI File $Revision: /main/1 $
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// Checkin $Date: August 18, 2006 13:52:13 $
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//###########################################################################
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//
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// FILE: DSP2833x_EQep.h
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//
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// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
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// Register Bit Definitions.
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//
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//###########################################################################
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// $TI Release: 2833x/2823x Header Files V1.32 $
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// $Release Date: June 28, 2010 $
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// $Copyright:
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// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef DSP2833x_EQEP_H
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#define DSP2833x_EQEP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// Capture decoder control register bit definitions
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//
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struct QDECCTL_BITS { // bits description
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Uint16 rsvd1:5; // 4:0 reserved
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Uint16 QSP:1; // 5 QEPS input polarity
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Uint16 QIP:1; // 6 QEPI input polarity
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Uint16 QBP:1; // 7 QEPB input polarity
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Uint16 QAP:1; // 8 QEPA input polarity
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Uint16 IGATE:1; // 9 Index pulse gating option
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Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
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Uint16 XCR:1; // 11 External clock rate
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Uint16 SPSEL:1; // 12 Sync output pin select
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Uint16 SOEN:1; // 13 Enable position compare sync
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Uint16 QSRC:2; // 15:14 Position counter source
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};
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union QDECCTL_REG {
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Uint16 all;
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struct QDECCTL_BITS bit;
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};
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//
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// QEP control register bit definitions
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//
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struct QEPCTL_BITS { // bits description
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Uint16 WDE:1; // 0 QEP watchdog enable
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Uint16 UTE:1; // 1 QEP unit timer enable
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Uint16 QCLM:1; // 2 QEP capture latch mode
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Uint16 QPEN:1; // 3 Quadrature position counter enable
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Uint16 IEL:2; // 5:4 Index event latch
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Uint16 SEL:1; // 6 Strobe event latch
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Uint16 SWI:1; // 7 Software init position counter
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Uint16 IEI:2; // 9:8 Index event init of position count
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Uint16 SEI:2; // 11:10 Strobe event init
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Uint16 PCRM:2; // 13:12 Position counter reset
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Uint16 FREE_SOFT:2; // 15:14 Emulation mode
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};
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union QEPCTL_REG {
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Uint16 all;
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struct QEPCTL_BITS bit;
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};
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//
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// Quadrature capture control register bit definitions
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//
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struct QCAPCTL_BITS { // bits description
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Uint16 UPPS:4; // 3:0 Unit position pre-scale
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Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
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Uint16 rsvd1:8; // 14:7 reserved
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Uint16 CEN:1; // 15 Enable QEP capture
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};
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union QCAPCTL_REG {
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Uint16 all;
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struct QCAPCTL_BITS bit;
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};
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//
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// Position compare control register bit definitions
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//
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struct QPOSCTL_BITS { // bits description
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Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
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Uint16 PCE:1; // 12 Position compare enable/disable
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Uint16 PCPOL:1; // 13 Polarity of sync output
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Uint16 PCLOAD:1; // 14 Position compare of shadow load
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Uint16 PCSHDW:1; // 15 Position compare shadow enable
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};
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union QPOSCTL_REG {
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Uint16 all;
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struct QPOSCTL_BITS bit;
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};
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//
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// QEP interrupt control register bit definitions
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//
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struct QEINT_BITS { // bits description
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Uint16 rsvd1:1; // 0 reserved
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Uint16 PCE:1; // 1 Position counter error
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Uint16 QPE:1; // 2 Quadrature phase error
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Uint16 QDC:1; // 3 Quadrature dir change
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Uint16 WTO:1; // 4 Watchdog timeout
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Uint16 PCU:1; // 5 Position counter underflow
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Uint16 PCO:1; // 6 Position counter overflow
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Uint16 PCR:1; // 7 Position compare ready
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Uint16 PCM:1; // 8 Position compare match
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Uint16 SEL:1; // 9 Strobe event latch
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Uint16 IEL:1; // 10 Event latch
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Uint16 UTO:1; // 11 Unit timeout
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Uint16 rsvd2:4; // 15:12 reserved
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};
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union QEINT_REG {
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Uint16 all;
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struct QEINT_BITS bit;
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};
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//
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// QEP interrupt status register bit definitions
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//
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struct QFLG_BITS { // bits description
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Uint16 INT:1; // 0 Global interrupt
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Uint16 PCE:1; // 1 Position counter error
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Uint16 PHE:1; // 2 Quadrature phase error
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Uint16 QDC:1; // 3 Quadrature dir change
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Uint16 WTO:1; // 4 Watchdog timeout
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Uint16 PCU:1; // 5 Position counter underflow
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Uint16 PCO:1; // 6 Position counter overflow
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Uint16 PCR:1; // 7 Position compare ready
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Uint16 PCM:1; // 8 Position compare match
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Uint16 SEL:1; // 9 Strobe event latch
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Uint16 IEL:1; // 10 Event latch
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Uint16 UTO:1; // 11 Unit timeout
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Uint16 rsvd2:4; // 15:12 reserved
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};
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union QFLG_REG {
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Uint16 all;
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struct QFLG_BITS bit;
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};
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//
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// QEP interrupt force register bit definitions
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//
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struct QFRC_BITS { // bits description
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Uint16 reserved:1; // 0 Reserved
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Uint16 PCE:1; // 1 Position counter error
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Uint16 PHE:1; // 2 Quadrature phase error
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Uint16 QDC:1; // 3 Quadrature dir change
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Uint16 WTO:1; // 4 Watchdog timeout
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Uint16 PCU:1; // 5 Position counter underflow
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Uint16 PCO:1; // 6 Position counter overflow
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Uint16 PCR:1; // 7 Position compare ready
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Uint16 PCM:1; // 8 Position compare match
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Uint16 SEL:1; // 9 Strobe event latch
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Uint16 IEL:1; // 10 Event latch
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Uint16 UTO:1; // 11 Unit timeout
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Uint16 rsvd2:4; // 15:12 reserved
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};
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union QFRC_REG {
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Uint16 all;
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struct QFRC_BITS bit;
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};
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//
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// V1.1 Added UPEVNT (bit 7) This reflects changes
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// made as of F2833x Rev A devices
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//
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//
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// QEP status register bit definitions
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//
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struct QEPSTS_BITS { // bits description
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Uint16 PCEF:1; // 0 Position counter error
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Uint16 FIMF:1; // 1 First index marker
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Uint16 CDEF:1; // 2 Capture direction error
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Uint16 COEF:1; // 3 Capture overflow error
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Uint16 QDLF:1; // 4 QEP direction latch
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Uint16 QDF:1; // 5 Quadrature direction
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Uint16 FIDF:1; // 6 Direction on first index marker
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Uint16 UPEVNT:1; // 7 Unit position event flag
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Uint16 rsvd1:8; // 15:8 reserved
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};
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union QEPSTS_REG {
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Uint16 all;
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struct QEPSTS_BITS bit;
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};
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struct EQEP_REGS {
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Uint32 QPOSCNT; // Position counter
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Uint32 QPOSINIT; // Position counter init
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Uint32 QPOSMAX; // Maximum position count
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Uint32 QPOSCMP; // Position compare
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Uint32 QPOSILAT; // Index position latch
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Uint32 QPOSSLAT; // Strobe position latch
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Uint32 QPOSLAT; // Position latch
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Uint32 QUTMR; // Unit timer
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Uint32 QUPRD; // Unit period
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Uint16 QWDTMR; // QEP watchdog timer
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Uint16 QWDPRD; // QEP watchdog period
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union QDECCTL_REG QDECCTL; // Quadrature decoder control
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union QEPCTL_REG QEPCTL; // QEP control
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union QCAPCTL_REG QCAPCTL; // Quadrature capture control
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union QPOSCTL_REG QPOSCTL; // Position compare control
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union QEINT_REG QEINT; // QEP interrupt control
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union QFLG_REG QFLG; // QEP interrupt flag
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union QFLG_REG QCLR; // QEP interrupt clear
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union QFRC_REG QFRC; // QEP interrupt force
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union QEPSTS_REG QEPSTS; // QEP status
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Uint16 QCTMR; // QEP capture timer
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Uint16 QCPRD; // QEP capture period
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Uint16 QCTMRLAT; // QEP capture latch
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Uint16 QCPRDLAT; // QEP capture period latch
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Uint16 rsvd1[30]; // reserved
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};
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//
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// GPI/O External References & Function Declarations
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//
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extern volatile struct EQEP_REGS EQep1Regs;
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extern volatile struct EQEP_REGS EQep2Regs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_EQEP_H definition
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//
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// End of file
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//
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